Issued Patents 2019
Showing 1–25 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510617 | CMOS VFET contacts with trench solid and liquid phase epitaxy | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2019-12-17 |
| 10490653 | Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors | Su Chen Fan, Zuoguang Liu, Heng Wu | 2019-11-26 |
| 10468525 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2019-11-05 |
| 10453922 | Conformal doping for punch through stopper in fin field effect transistor devices | Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie | 2019-10-22 |
| 10453939 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2019-10-22 |
| 10439031 | Integration of vertical-transport transistors and electrical fuses | Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh | 2019-10-08 |
| 10439045 | Flipped VFET with self-aligned junctions and controlled gate length | Chen Zhang | 2019-10-08 |
| 10418277 | Air gap spacer formation for nano-scale semiconductor devices | Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta +2 more | 2019-09-17 |
| 10418485 | Forming a combination of long channel devices and vertical transport Fin field effect transistors on the same substrate | Cheng Chi, Chen Zhang | 2019-09-17 |
| 10411127 | Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate | Cheng Chi, Chen Zhang | 2019-09-10 |
| 10396177 | Prevention of extension narrowing in nanosheet field effect transistors | Chun Wing Yeung, Chen Zhang | 2019-08-27 |
| 10396178 | Method of forming improved vertical FET process with controlled gate length and self-aligned junctions | Chen Zhang | 2019-08-27 |
| 10396000 | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions | Chun-Chen Yeh, Hui Zang | 2019-08-27 |
| 10396183 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Chun-Chen Yeh, Hui Zang | 2019-08-27 |
| 10396208 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Ruilong Xie, Chun-Chen Yeh | 2019-08-27 |
| 10388731 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Xin Miao, Ruilong Xie | 2019-08-20 |
| 10388754 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2019-08-20 |
| 10388768 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Chun-Chen Yeh, Hui Zang | 2019-08-20 |
| 10388769 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Chun-Chen Yeh, Hui Zang | 2019-08-20 |
| 10381273 | Vertically stacked multi-channel transistor structure | Kangguo Cheng, Chun-Chen Yeh, Ruilong Xie | 2019-08-13 |
| 10381346 | Logic gate designs for 3D monolithic direct stacked VTFET | Chen Zhang, Terence B. Hook | 2019-08-13 |
| 10374064 | Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping | Kangguo Cheng, Ruilong Xie | 2019-08-06 |
| 10374060 | VFET bottom epitaxy formed with anchors | Chen Zhang | 2019-08-06 |
| 10367069 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2019-07-30 |
| 10366931 | Nanosheet devices with CMOS epitaxy and method of forming | Ruilong Xie, Cheng Chi, Pietro Montanini, Nicolas Loubet | 2019-07-30 |