Issued Patents 2019
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510617 | CMOS VFET contacts with trench solid and liquid phase epitaxy | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Tenko Yamashita | 2019-12-17 |
| 10504997 | Silicon-germanium Fin structure having silicon-rich outer surface | Hemanth Jagannathan, Choonghyun Lee, Koji Watanabe | 2019-12-10 |
| 10490667 | Three-dimensional field effect device | Huimei Zhou, Su Chen Fan, Peng Xu, Nicolas Loubet | 2019-11-26 |
| 10475923 | Method and structure for forming vertical transistors with various gate lengths | Kangguo Cheng, Choonghyun Lee, Juntao Li | 2019-11-12 |
| 10461154 | Bottom isolation for nanosheet transistors on bulk substrate | Yi Song, Chi-Chun Liu, Zhenxing Bi | 2019-10-29 |
| 10453824 | Structure and method to form nanosheet devices with bottom isolation | Chun Wing Yeung | 2019-10-22 |
| 10453940 | Vertical field effect transistor with strained channel region extension | Choonghyun Lee, Juntao Li, Kangguo Cheng | 2019-10-22 |
| 10439049 | Nanosheet device with close source drain proximity | Veeraraghavan S. Basker, Alexander Reznicek | 2019-10-08 |
| 10439063 | Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices | Alexander Reznicek, Jingyun Zhang, Xin Miao | 2019-10-08 |
| 10439043 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2019-10-08 |
| 10431503 | Sacrificial cap for forming semiconductor contact | Praneet Adusumilli, Zuoguang Liu, Jie Yang, Chun Wing Yeung | 2019-10-01 |
| 10431502 | Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact | Choonghyun Lee, Chun Wing Yeung, Hemanth Jagannathan | 2019-10-01 |
| 10418288 | Techniques for forming different gate length vertical transistors with dual gate oxide | Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung | 2019-09-17 |
| 10411120 | Self-aligned inner-spacer replacement process using implantation | Robin Hsin Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Chun Wing Yeung | 2019-09-10 |
| 10388766 | Vertical transport FET (VFET) with dual top spacer | Michael P. Belyansky, Choonghyun Lee | 2019-08-20 |
| 10381479 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell +3 more | 2019-08-13 |
| 10381442 | Low resistance source drain contact formation | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Chun-Chen Yeh | 2019-08-13 |
| 10361306 | High acceptor level doping in silicon germanium | Mona A. Ebrish, Oleg Gluschenkov, Alexander Reznicek | 2019-07-23 |
| 10347581 | Contact formation in semiconductor devices | Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Hiroaki Niimi | 2019-07-09 |
| 10340363 | Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers | Choonghyun Lee | 2019-07-02 |
| 10333000 | Forming strained channel with germanium condensation | Kangguo Cheng, Jie Yang | 2019-06-25 |
| 10326017 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Junli Wang | 2019-06-18 |
| 10325815 | Vertical transport fin field effect transistors having different channel lengths | Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung | 2019-06-18 |
| 10319836 | Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy | Alexander Reznicek | 2019-06-11 |
| 10319643 | Vertical FET with strained channel | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2019-06-11 |