Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10388789 | Reducing series resistance between source and/or drain regions and a channel region | Oleg Gluschenkov | 2019-08-20 |
| 10381348 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Deepika Priyadarshini +2 more | 2019-08-13 |
| 10361127 | Vertical transport FET with two or more gate lengths | Gauri Karve, Fee Li Lie, Indira Seshadri, Leigh Anne H. Clevenger, Ekmini Anuja De Silva +1 more | 2019-07-23 |
| 10361306 | High acceptor level doping in silicon germanium | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2019-07-23 |
| 10319855 | Reducing series resistance between source and/or drain regions and a channel region | Oleg Gluschenkov | 2019-06-11 |
| 10229910 | Separate N and P fin etching for reduced CMOS device leakage | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more | 2019-03-12 |