Issued Patents 2019
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522342 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Isaac Lauer, Xin Miao | 2019-12-31 |
| 10497779 | Stacked nanowire semiconductor device | William L. Nicoll, Hanfei Wang | 2019-12-03 |
| 10438956 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-10-08 |
| 10429743 | Optical mask validation | Daniel A. Corliss, Derren N. Dunn, Shawn P. Fetterolf | 2019-10-01 |
| 10411120 | Self-aligned inner-spacer replacement process using implantation | Robin Hsin Kuo Chao, Chi-Chun Liu, Shogo Mochizuki, Chun Wing Yeung | 2019-09-10 |
| 10395922 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Isaac Lauer, Xin Miao | 2019-08-27 |
| 10367062 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Isaac Lauer, Nicolas Loubet | 2019-07-30 |
| 10340340 | Multiple-threshold nanosheet transistors | Ruqiang Bao, Terence B. Hook, Nicolas Loubet, Robert R. Robison, Reinaldo Vega +1 more | 2019-07-02 |
| 10325983 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Isaac Lauer, Xin Miao | 2019-06-18 |
| 10312321 | Trigate device with full silicided epi-less source/drain for high density access transistor applications | Fei Liu, Zhen Zhang | 2019-06-04 |
| 10297512 | Method of making thin SRAM cell having vertical transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-05-21 |
| 10276695 | Self-aligned inner-spacer replacement process using implantation | Robin Hsin Kuo Chao, Chi-Chun Liu, Shogo Mochizuki, Chun Wing Yeung | 2019-04-30 |
| 10256139 | Chemoepitaxy etch trim using a self aligned hard mask for metal line to via | Markus Brink, Chung-Hsun Lin, HsinYu Tsai | 2019-04-09 |
| 10249739 | Nanosheet MOSFET with partial release and source/drain epitaxy | Terence B. Hook, Nicolas Loubet, Robert R. Robison, Reinaldo Vega | 2019-04-02 |
| 10242920 | Integrating and isolating NFET and PFET nanosheet transistors on a substrate | Nicolas Loubet, Muthumanickam Sankarapandian | 2019-03-26 |
| 10229917 | Thin SRAM cell having vertical transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-03-12 |
| 10217817 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Isaac Lauer, Xin Miao | 2019-02-26 |
| 10177226 | Preventing threshold voltage variability in stacked nanosheets | Nicolas Loubet | 2019-01-08 |
| 10170608 | Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET | Szu-Lin Cheng, Gen P. Lauer, Isaac Lauer | 2019-01-01 |
| 10170584 | Nanosheet field effect transistors with partial inside spacers | Terence B. Hook, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla | 2019-01-01 |
| 10170485 | Three-dimensional stacked junctionless channels for dense SRAM | Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla | 2019-01-01 |
| 10170552 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Isaac Lauer, Nicolas Loubet | 2019-01-01 |
| 10170679 | Josephson junction with spacer | Josephine B. Chang, Ryan M. Martin, Jeffrey W. Sleight | 2019-01-01 |
| 10170636 | Gate-to-bulk substrate isolation in gate-all-around devices | Josephine B. Chang, Isaac Lauer, Xin Miao | 2019-01-01 |
| 10170634 | Wire-last gate-all-around nanowire FET | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2019-01-01 |