Issued Patents 2019
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10483344 | Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers | Son V. Nguyen | 2019-11-19 |
| 10461148 | Multilayer buried metal-insultor-metal capacitor structures | Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli | 2019-10-29 |
| 10446606 | Back-side memory element with local memory select transistor | Arvind Kumar | 2019-10-15 |
| 10373874 | Middle of the line subtractive self-aligned contacts | Balasubramanian Pranatharthiharan | 2019-08-06 |
| 10332959 | Bulk to silicon on insulator device | Terence B. Hook, Tenko Yamashita | 2019-06-25 |
| 10325821 | Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus | Terry Hook, Ardasheir Rahman, Chen Zhang | 2019-06-18 |
| 10283411 | Stacked vertical transistor device for three-dimensional monolithic integration | Terence B. Hook | 2019-05-07 |
| 10243043 | Self-aligned air gap spacer for nanosheet CMOS devices | Shogo Mochizuki, Alexander Reznicek, Junli Wang | 2019-03-26 |
| 10229915 | Mirror contact capacitor | Terence B. Hook, Tenko Yamashita | 2019-03-12 |
| 10217674 | Three-dimensional monolithic vertical field effect transistor logic gates | Terry Hook, Ardasheir Rahman, Chen Zhang | 2019-02-26 |
| 10211341 | Tensile strained high percentage silicon germanium alloy FinFETS | Bruce B. Doris, Pouya Hashemi, Alexander Reznicek, Robin M. Schulz | 2019-02-19 |
| 10199352 | Wafer bonding edge protection using double patterning with edge exposure | — | 2019-02-05 |
| 10192888 | Metallized junction FinFET structures | Bruce B. Doris, Pranita Kerber, Alexander Reznicek | 2019-01-29 |