Issued Patents 2019
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522538 | Using source/drain contact cap during gate cut | Haiting Wang, Shesh Mani Pandey, Laertis Economikos, Hui Zang, Ruilong Xie +2 more | 2019-12-31 |
| 10510613 | Contact structures | Xusheng Wu, Haigou Huang, John H. Zhang, Pei Liu, Laertis Economikos | 2019-12-17 |
| 10475791 | Transistor fins with different thickness gate dielectric | Hui Zang, Garo Derderian, Laertis Economikos, Chun Yu Wong, Shesh Mani Pandey | 2019-11-12 |
| 10475693 | Method for forming single diffusion breaks between finFET devices and the resulting devices | Hong Yu, Jinping Liu, Hui Zang | 2019-11-12 |
| 10453936 | Methods of forming replacement gate structures on transistor devices | Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Yang, Jinping Liu +1 more | 2019-10-22 |
| 10446395 | Self-aligned multiple patterning processes with layered mandrels | Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu, Hui Zang | 2019-10-15 |
| 10431500 | Multi-step insulator formation in trenches to avoid seams in insulators | Asli Sirman, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu | 2019-10-01 |
| 10418272 | Methods, apparatus, and system for a semiconductor device comprising gates with short heights | Garo Derderian, Hui Zang, John H. Zhang, Haigou Huang, Jinping Liu | 2019-09-17 |
| 10403742 | Field-effect transistors with fins formed by a damascene-like process | Wei Zhao, Haiting Wang, David Paul Brunco, Shesh Mani Pandey, Jinping Liu +1 more | 2019-09-03 |
| 10347541 | Active gate contacts and method of fabrication thereof | David Paul Brunco, Pei Liu, Shariq Siddiqui, Jinping Liu | 2019-07-09 |
| 10340183 | Cobalt plated via integration scheme | Qiang Fang, Shafaat Ahmed, Zhiguo Sun, Dinesh R. Koli, Wei-Tsu Tseng | 2019-07-02 |
| 10340142 | Methods, apparatus and system for self-aligned metal hard masks | Jinsheng Gao, Daniel Jaeger, Michael V. Aquilino, Patrick Carpenter, Pei Liu +1 more | 2019-07-02 |
| 10276374 | Methods for forming fins | Garo Derderian, Jinping Liu | 2019-04-30 |
| 10249496 | Narrowed feature formation during a double patterning process | Xusheng Yu, John H. Zhang, Xiaoqiang Zhang | 2019-04-02 |
| 10236213 | Gate cut structure with liner spacer and related method | Shesh Mani Pandey, Hui Zang, Laertis Economikos | 2019-03-19 |
| 10229999 | Methods of forming upper source/drain regions on a vertical transistor device | Xusheng Wu, John H. Zhang, Haigou Huang | 2019-03-12 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven R. Soss +8 more | 2019-02-26 |
| 10199265 | Variable space mandrel cut for self aligned double patterning | Byoung Youp Kim, Jinping Liu | 2019-02-05 |
| 10192791 | Semiconductor devices with robust low-k sidewall spacers and method for producing the same | Man Gu, Tao Han, Junsic Hong, Asli Sirman, Charlotte DeWan Adams +2 more | 2019-01-29 |
| 10192780 | Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks | Xiaohan Wang, Brendan O'Brien, Terry A. Spooner, Jinping Liu, Ravi Prakash Srivastava | 2019-01-29 |