Issued Patents 2019
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522538 | Using source/drain contact cap during gate cut | Haiting Wang, Jiehui Shu, Laertis Economikos, Hui Zang, Ruilong Xie +2 more | 2019-12-31 |
| 10475791 | Transistor fins with different thickness gate dielectric | Hui Zang, Garo Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu | 2019-11-12 |
| 10403742 | Field-effect transistors with fins formed by a damascene-like process | Wei Zhao, Haiting Wang, David Paul Brunco, Jiehui Shu, Jinping Liu +1 more | 2019-09-03 |
| 10374029 | Semiconductor device resistor structure | Hui Zang, Josef S. Watts | 2019-08-06 |
| 10361289 | Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same | Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu +4 more | 2019-07-23 |
| 10355104 | Single-curvature cavity for semiconductor epitaxy | Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao +3 more | 2019-07-16 |
| 10347748 | Methods of forming source/drain regions on FinFET devices | Muhammad Tawhidur Rahman, Srikanth B. Samavedam | 2019-07-09 |
| 10236213 | Gate cut structure with liner spacer and related method | Jiehui Shu, Hui Zang, Laertis Economikos | 2019-03-19 |