Issued Patents 2019
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510610 | Structure and method of forming fin device having improved fin liner | Naushad K. Variam, Sony Varghese, Johannes M. van Meer, Jae-Young Lee | 2019-12-17 |
| 10510870 | Techniques for forming device having etch-resistant isolation oxide | Sony Varghese, Jae-Young Lee, Johannes M. van Meer | 2019-12-17 |
| 10497798 | Vertical field effect transistor with self-aligned contacts | Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Lars Liebmann +2 more | 2019-12-03 |
| 10461196 | Control of length in gate region during processing of VFET structures | Chanro Park, Steven Bentley, Ruilong Xie | 2019-10-29 |
| 10446653 | Transistor-based semiconductor device with air-gap spacers and gate contact over active area | Ruilong Xie, Chanro Park, Lars Liebmann, Hoon Kim | 2019-10-15 |
| 10446399 | Hard mask layer to reduce loss of isolation material during dummy gate removal | Ruilong Xie, Chanro Park, Hoon Kim | 2019-10-15 |
| 10410933 | Replacement metal gate patterning for nanosheet devices | Ruilong Xie, Chanro Park, Hoon Kim, Hui Zang, Guowei Xu | 2019-09-10 |
| 10403552 | Replacement gate formation with angled etch and deposition | Naushad K. Variam, Sony Varghese, Johannes M. van Meer, Jae-Young Lee | 2019-09-03 |
| 10403738 | Techniques for improved spacer in nanosheet device | Rajesh Prasad, John Hautala, Sony Varghese | 2019-09-03 |
| 10403547 | Structure and method of forming self aligned contacts in semiconductor device | — | 2019-09-03 |
| 10388652 | Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same | Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann +4 more | 2019-08-20 |
| 10388745 | Structure and method of forming transistor device having improved gate contact arrangement | — | 2019-08-20 |
| 10381272 | Techniques for forming multiple work function nanosheet device | — | 2019-08-13 |
| 10366930 | Self-aligned gate cut isolation | Ruilong Xie, Chanro Park, Kangguo Cheng, Guillaume Bouche | 2019-07-30 |
| 10319627 | Air-gap spacers for field-effect transistors | Chanro Park, Hoon Kim, Ruilong Xie | 2019-06-11 |
| 10312154 | Method of forming vertical FinFET device having self-aligned contacts | Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Lars Liebmann +2 more | 2019-06-04 |
| 10297597 | Composite isolation structures for a fin-type field effect transistor | Ruilong Xie, Chanro Park, Murat Kerem Akarvardar | 2019-05-21 |
| 10290549 | Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same | Ruilong Xie, Julien Frougier, Edward J. Nowak, Nigel G. Cave, Lars Liebmann +2 more | 2019-05-14 |
| 10283617 | Hybrid spacer integration for field-effect transistors | Ruilong Xie, Dong-Ick Lee, Chanro Park | 2019-05-07 |
| 10236291 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Chanro Park, Hoon Kim, Ruilong Xie, Kwan-Yong Lim | 2019-03-19 |
| 10229855 | Methods of forming transistor devices with different threshold voltages and the resulting devices | Hoon Kim, Ruilong Xie, Chanro Park | 2019-03-12 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Chanro Park, Steven R. Soss, Hui Zang +8 more | 2019-02-26 |
| 10177041 | Fin-type field effect transistors (FINFETS) with replacement metal gates and methods | Ruilong Xie, Laertis Economikos, Chanro Park | 2019-01-08 |
| 10177241 | Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor | Chanro Park, Ruilong Xie, Hoon Kim | 2019-01-08 |
| 10176996 | Replacement metal gate and fabrication process with reduced lithography steps | Chanro Park, Hoon Kim | 2019-01-08 |