Issued Patents 2019
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522679 | Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures | Ashish Jha, Hong Yu, Xinyuan Dou, Dongil Choi, Edmund K. Banghart +1 more | 2019-12-31 |
| 10510613 | Contact structures | Jiehui Shu, Haigou Huang, John H. Zhang, Pei Liu, Laertis Economikos | 2019-12-17 |
| 10483369 | Methods of forming replacement gate structures on transistor devices | Haigou Huang, Jinsheng Gao | 2019-11-19 |
| 10468310 | Spacer integration scheme for FNET and PFET devices | Jianwei Peng | 2019-11-05 |
| 10461155 | Epitaxial region for embedded source/drain region having uniform thickness | Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Joo Tat Ong, Wei Hong +6 more | 2019-10-29 |
| 10446683 | Methods, apparatus and system for forming sigma shaped source/drain lattice | Hong Yu | 2019-10-15 |
| 10446483 | Metal-insulator-metal capacitors with enlarged contact areas | Sipeng Gu, Jianwei Peng, Yi Qi, Jeffrey Chee | 2019-10-15 |
| 10439026 | Fins with single diffusion break facet improvement using epitaxial insulator | Chun Yu Wong, Hui Zang | 2019-10-08 |
| 10388562 | Composite contact etch stop layer | Haigou Huang, Daniel Jaeger, Jinsheng Gao | 2019-08-20 |
| 10347729 | Device for improving performance through gate cut last process | Haigou Huang | 2019-07-09 |
| 10347531 | Middle of the line (MOL) contact formation method and structure | Sipeng Gu, Xinyuan Dou, Xiaobo Chen, Guoliang Zhu, Wenhe Lin +1 more | 2019-07-09 |
| 10347740 | Fin structures and multi-Vt scheme based on tapered fin and method to form | Min-hwa Chi, Edmund K. Banghart | 2019-07-09 |
| 10236218 | Methods, apparatus and system for forming wrap-around contact with dual silicide | Ruilong Xie, Julien Frougier, Hiroaki Niimi, Nigel G. Cave | 2019-03-19 |
| 10229999 | Methods of forming upper source/drain regions on a vertical transistor device | John H. Zhang, Haigou Huang, Jiehui Shu | 2019-03-12 |
| 10224418 | Integrated circuit fabrication with boron etch-stop layer | Chengwen Pei, Ziyan Xu | 2019-03-05 |
| 10224330 | Self-aligned junction structures | Jianwei Peng | 2019-03-05 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven R. Soss +8 more | 2019-02-26 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Jianwei Peng, Sipeng Gu, Hsien-Ching Lo | 2019-02-19 |
| 10204991 | Transistor structures and fabrication methods thereof | Jin Ping Liu, Min-hwa Chi | 2019-02-12 |
| 10181468 | Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming | Ziyan Xu, Chengwen Pei | 2019-01-15 |
| 10176995 | Methods, apparatus and system for gate cut process using a stress material in a finFET device | Haigou Huang | 2019-01-08 |