Issued Patents 2019
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10468310 | Spacer integration scheme for FNET and PFET devices | Xusheng Wu | 2019-11-05 |
| 10453754 | Diffused contact extension dopants in a transistor device | Haigou Huang, Qun Gao, Xin Wang | 2019-10-22 |
| 10446483 | Metal-insulator-metal capacitors with enlarged contact areas | Sipeng Gu, Xusheng Wu, Yi Qi, Jeffrey Chee | 2019-10-15 |
| 10431665 | Multiple-layer spacers for field-effect transistors | Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo | 2019-10-01 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie | 2019-09-10 |
| 10297675 | Dual-curvature cavity for epitaxial semiconductor growth | Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianghu Yan, Yi Qi | 2019-05-21 |
| 10276689 | Method of forming a vertical field effect transistor (VFET) and a VFET structure | Yi Qi, Hsien-Ching Lo, Ruilong Xie, Xunyuan Zhang, Hui Zang | 2019-04-30 |
| 10262903 | Boundary spacer structure and integration | Judson R. Holt, Yi Qi, Hsien-Ching Lo | 2019-04-16 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Hsien-Ching Lo, Wei Hong, Yanping Shen, Yongjun Shi +5 more | 2019-04-02 |
| 10224330 | Self-aligned junction structures | Xusheng Wu | 2019-03-05 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Xusheng Wu, Sipeng Gu, Hsien-Ching Lo | 2019-02-19 |