Issued Patents 2019
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu +3 more | 2019-11-12 |
| 10418365 | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array | Hui Zang, Rinus Tek Po Lee | 2019-09-17 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Ruilong Xie | 2019-09-10 |
| 10373877 | Methods of forming source/drain contact structures on integrated circuit products | Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong +3 more | 2019-08-06 |
| 10290712 | LDMOS finFET structures with shallow trench isolation inside the fin | Jagar Singh, Hui Zang | 2019-05-14 |
| 10211206 | Two-port vertical SRAM circuit structure and method for producing the same | Hui Zang | 2019-02-19 |