Issued Patents 2019
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Scott Beasor +3 more | 2019-11-12 |
| 10431665 | Multiple-layer spacers for field-effect transistors | Tao Han, Jinping Liu, Hsien-Ching Lo, Jianwei Peng | 2019-10-01 |
| 10396206 | Gate cut method | Ashish Jha, Haiting Wang, Wei Hong, Wei Zhao, Tae Jeong LEE | 2019-08-27 |
| 10355104 | Single-curvature cavity for semiconductor epitaxy | Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao +3 more | 2019-07-16 |
| 10326002 | Self-aligned gate contact and cross-coupling contact formation | Hui Zang, Ruilong Xie, Scott Beasor | 2019-06-18 |
| 10192746 | STI inner spacer to mitigate SDB loading | Ashish Jha, Hui Zhan, Hong Yu, Haiting Wang, Edward Reis +1 more | 2019-01-29 |