Issued Patents 2019
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10483283 | Flash memory device and manufacture thereof | Shan Li, Sheng Fen Chiu | 2019-11-19 |
| 10475899 | Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby | Ruilong Xie, Andreas Knorr, Julien Frougier, Hui Zang | 2019-11-12 |
| 10438955 | Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods | Hui Zang | 2019-10-08 |
| 10396155 | Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region | Hui Zang | 2019-08-27 |
| 10388790 | FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming | Ajey Poovannummoottil Jacob, Abhijeet Paul | 2019-08-20 |
| 10347740 | Fin structures and multi-Vt scheme based on tapered fin and method to form | Xusheng Wu, Edmund K. Banghart | 2019-07-09 |
| 10332834 | Semiconductor fuses with nanowire fuse links and fabrication methods thereof | Chun Yu Wong, Jagar Singh, Ashish Baraskar | 2019-06-25 |
| 10297609 | Flash memory device and manufacture thereof | Shan Li, Sheng Fen Chiu | 2019-05-21 |
| 10290654 | Circuit structures with vertically spaced transistors and fabrication methods | Hui Zang, Manfred Eller | 2019-05-14 |
| 10290634 | Multiple threshold voltages using fin pitch and profile | Wen-Pin Peng | 2019-05-14 |
| 10276390 | Method and apparatus for reducing threshold voltage mismatch in an integrated circuit | Meixiong Zhao, Kuniko Kikuta | 2019-04-30 |
| 10269811 | Selective SAC capping on fin field effect transistor structures and related methods | Hui Zang | 2019-04-23 |
| 10243059 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Manfred Eller, Hui Zang | 2019-03-26 |
| 10204991 | Transistor structures and fabrication methods thereof | Xusheng Wu, Jin Ping Liu | 2019-02-12 |
| 10177157 | Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate | Hui Zang | 2019-01-08 |
| 10170353 | Devices and methods for dynamically tunable biasing to backplates and wells | Hui Zang | 2019-01-01 |
| 10170377 | Memory cell with recessed source/drain contacts to reduce capacitance | Hui Zang | 2019-01-01 |
| 10170315 | Semiconductor device having local buried oxide | Yanxiang Liu | 2019-01-01 |