Issued Patents 2019
Showing 176–200 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10319731 | Integrated circuit structure having VFET and embedded memory structure and method of forming same | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2019-06-11 |
| 10319638 | Self-aligned contact cap | Peng Xu | 2019-06-11 |
| 10319640 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-11 |
| 10319643 | Vertical FET with strained channel | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2019-06-11 |
| 10319645 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2019-06-11 |
| 10319677 | Fabrication of vertical fuses from vertical fins | James J. Demarest, Juntao Li | 2019-06-11 |
| 10319717 | Forming on-chip metal-insulator-semiconductor capacitor with pillars | Zhenxing Bi, Peng Xu, Chen Zhang | 2019-06-11 |
| 10319813 | Nanosheet CMOS transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-11 |
| 10312104 | Sacrificial mandrel structure with oxide pillars having different widths and resulting fins arrangements | — | 2019-06-04 |
| 10312370 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2019-06-04 |
| 10312350 | Nanosheet with changing SiGe percentage for SiGe lateral recess | Xin Miao, Wenyu Xu, Chen Zhang | 2019-06-04 |
| 10312337 | Fabrication of nano-sheet transistors with different threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-06-04 |
| 10312325 | Techniques for forming finFET transistors with same fin pitch and different source/drain epitaxy configurations | Peng Xu | 2019-06-04 |
| 10312323 | Bulk nanosheet with dielectric isolation | Bruce B. Doris, Junli Wang | 2019-06-04 |
| 10312318 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-04 |
| 10312148 | Method and structure for forming MOSFET with reduced parasitic capacitance | Peng Xu, Chen Zhang | 2019-06-04 |
| 10312132 | Forming sacrificial endpoint layer for deep STI recess | Juntao Li, Sebastian Naczas, Peng Xu | 2019-06-04 |
| 10304742 | Forming insulator fin structure in isolation region to support gate structures | Peng Xu | 2019-05-28 |
| 10304944 | Semiconductor structure with an L-shaped bottom | Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi | 2019-05-28 |
| 10304941 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-05-28 |
| 10304736 | Self-aligned contact | Xin Miao, Wenyu Xu, Chen Zhang | 2019-05-28 |
| 10297452 | Methods of forming a gate contact structure for a transistor | Ruilong Xie, Hui Zang, Tenko Yamashita, Chun-Chen Yeh | 2019-05-21 |
| 10297689 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-05-21 |
| 10297688 | Vertical field effect transistor with improved reliability | Xin Miao, Philip J. Oldiges, Wenyu Xu, Chen Zhang | 2019-05-21 |
| 10297686 | Tapered vertical FET having III-V channel | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-05-21 |