Issued Patents 2019
Showing 251–275 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10249537 | Method and structure for forming FinFET CMOS with dual doped STI regions | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-04-02 |
| 10249529 | Channel silicon germanium formation method | Nicolas Degors, Shawn P. Fetterolf, Ahmet S. Ozcan | 2019-04-02 |
| 10242916 | Stress memorization technique for strain coupling enhancement in bulk FINFET device | Juntao Li, Chun-Chen Yeh | 2019-03-26 |
| 10243062 | Fabrication of a vertical fin field effect transistor having a consistent channel width | Juntao Li | 2019-03-26 |
| 10243061 | Nanosheet transistor | Juntao Li, Heng Wu, Peng Xu | 2019-03-26 |
| 10243054 | Integrating standard-gate and extended-gate nanosheet transistors on the same substrate | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-26 |
| 10243046 | Fully depleted silicon-on-insulator device formation | Shawn P. Fetterolf, Ahmet S. Ozcan | 2019-03-26 |
| 10243044 | FinFETs with high quality source/drain structures | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2019-03-26 |
| 10243042 | FinFET with reduced parasitic capacitance | Darsen D. Lu, Xin Miao, Tenko Yamashita | 2019-03-26 |
| 10242986 | Flipped vertical field-effect-transistor | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-26 |
| 10242983 | Semiconductor device with increased source/drain area | Chi-Chun Liu, Peng Xu, Jie Yang | 2019-03-26 |
| 10242980 | Semiconductor fin isolation by a well trapping fin portion | Henry K. Utomo, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang, Reinaldo Vega | 2019-03-26 |
| 10242881 | Self-aligned single dummy fin cut with tight pitch | Cheng Chi, Chi-Chun Liu, Peng Xu | 2019-03-26 |
| 10236363 | Vertical field-effect transistors with controlled dimensions | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2019-03-19 |
| 10236382 | Multiple finFET formation with epitaxy separation | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-19 |
| 10236381 | IFinFET | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-19 |
| 10236380 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236364 | Tunnel transistor | Peng Xu, Heng Wu, Zhenxing Bi | 2019-03-19 |
| 10236359 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236355 | Fabrication of a vertical fin field effect transistor with a reduced contact resistance | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-19 |
| 10236346 | Transistor having a high germanium percentage fin channel and a gradient source/drain junction doping profile | Zhenxing Bi, Peng Xu, Chen Zhang | 2019-03-19 |
| 10236293 | FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236290 | Method and structure for improving vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2019-03-19 |
| 10236289 | Approach to fabrication of an on-chip resistor with a field effect transistor | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236219 | VFET metal gate patterning for vertical transport field effect transistor | Brent A. Anderson, Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Junli Wang | 2019-03-19 |