Issued Patents 2019
Showing 301–325 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10217707 | Trench contact resistance reduction | Zhenxing Bi, Juntao Li, Peng Xu | 2019-02-26 |
| 10217672 | Vertical transistor devices with different effective gate lengths | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2019-02-26 |
| 10217634 | Fin patterns with varying spacing without fin cut | Marc A. Bergendahl, John R. Sporre, Sean Teehan | 2019-02-26 |
| 10211055 | Fin patterns with varying spacing without fin cut | Marc A. Bergendahl, John R. Sporre, Sean Teehan | 2019-02-19 |
| 10211320 | Fin cut without residual fin defects | Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis | 2019-02-19 |
| 10211302 | Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts | Peng Xu | 2019-02-19 |
| 10211288 | Vertical transistors with multiple gate lengths | Zhenxing Bi, Peng Xu, Zheng Xu | 2019-02-19 |
| 10211092 | Transistor with robust air spacer | Chanro Park | 2019-02-19 |
| 10209367 | Colorimetric radiation dosimetry | Qing Cao, Zhengwen Li, Fei Liu | 2019-02-19 |
| 10204836 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-02-12 |
| 10204916 | Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET) | Veeraraghavan S. Basker, Ali Khakifirooz | 2019-02-12 |
| 10204835 | Fabrication of a vertical fin field effect transistor with reduced dimensional variations | — | 2019-02-12 |
| 10199464 | Techniques for VFET top source/drain epitaxy | Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-02-05 |
| 10199503 | Under-channel gate transistors | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-02-05 |
| 10199480 | Controlling self-aligned gate length in vertical transistor replacement gate flow | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-02-05 |
| 10199278 | Vertical field effect transistor (FET) with controllable gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2019-02-05 |
| 10199220 | Semiconductor structure having insulator pillars and semiconductor material on substrate | Alexander Reznicek, Dominic J. Schepis, Bruce B. Doris, Pouya Hashemi | 2019-02-05 |
| 10177237 | Etch stop for airgap protection | Ruilong Xie, Tenko Yamashita | 2019-01-08 |
| 10177235 | Nano-sheet transistors with different threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-01-08 |
| 10177223 | FinFET with reduced parasitic capacitance | Darsen D. Lu, Xin Miao, Tenko Yamashita | 2019-01-08 |
| 10177168 | Fin field-effect transistor having an oxide layer under one or more of the plurality of fins | Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis | 2019-01-08 |
| 10177154 | Structure and method to prevent EPI short between trenches in FinFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim +5 more | 2019-01-08 |
| 10177046 | Vertical FET with different channel orientations for NFET and PFET | Xin Miao, Wenyu Xu, Chen Zhang | 2019-01-08 |
| 10177256 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-01-08 |
| 10170595 | Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch | Peng Xu | 2019-01-01 |