Issued Patents 2019
Showing 276–300 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10236214 | Vertical transistor with variable gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-19 |
| 10229857 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-03-12 |
| 10229996 | Strained stacked nanowire field-effect transistors (FETs) | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-03-12 |
| 10229987 | Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins | Zuoguang Liu, Ruilong Xie, Tenko Yamashita | 2019-03-12 |
| 10229985 | Vertical field-effect transistor with uniform bottom spacer | Juntao Li, Peng Xu, Heng Wu | 2019-03-12 |
| 10229983 | Methods and structures for forming field-effect transistors (FETs) with low-k spacers | Huiming Bu, Peng Xu | 2019-03-12 |
| 10229971 | Integration of thick and thin nanosheet transistors on a single chip | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-12 |
| 10229920 | One-time programmable vertical field-effect transistor | Qintao Zhang, Juntao Li, Geng Wang | 2019-03-12 |
| 10229919 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-12 |
| 10224246 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Hao Tang, Peng Xu | 2019-03-05 |
| 10224431 | Wrapped source/drain contacts with enhanced area | Zuoguang Liu, Heng Wu, Peng Xu | 2019-03-05 |
| 10224334 | Anti-fuse with reduced programming voltage | Juntao Li, Chengwen Pei, Geng Wang | 2019-03-05 |
| 10224329 | Forming gates with varying length using sidewall image transfer | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-05 |
| 10224277 | Dielectric thermal conductor for passivating eFuse and metal resistor | Qing Cao, Zhengwen Li, Fei Liu | 2019-03-05 |
| 10224247 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-05 |
| 10224207 | Forming a contact for a tall fin transistor | Ruilong Xie, Tenko Yamashita | 2019-03-05 |
| 10217658 | Method and structure for minimizing fin reveal variation in FinFET transistor | Zhenxing Bi, Juntao Li, Hao Tang | 2019-02-26 |
| 10217869 | Semiconductor structure including low-K spacer material | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie | 2019-02-26 |
| 10217868 | Airgap spacers | Zuoguang Liu, Chun Wing Yeung | 2019-02-26 |
| 10217867 | Uniform fin dimensions using fin cut hardmask | Peng Xu | 2019-02-26 |
| 10217845 | Vertical field effect transistors with bottom source/drain epitaxy | Xin Miao, Wenyu Xu, Chen Zhang | 2019-02-26 |
| 10217843 | Fabrication of vertical field effect transistor structure with strained channels | Juntao Li | 2019-02-26 |
| 10217841 | Forming an uniform L-shaped inner spacer for a vertical transport fin field effect transistor (VT FinFET) | Juntao Li, Peng Xu, Jingyun Zhang | 2019-02-26 |
| 10217840 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-02-26 |
| 10217818 | Method of formation of germanium nanowires on bulk substrates | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2019-02-26 |