Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522661 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2019-12-31 |
| 10388795 | Vertical transistor including controlled gate length and a self-aligned junction | Kangguo Cheng | 2019-08-20 |
| 10283602 | Fully depleted SOI device for reducing parasitic back gate capacitance | Kangguo Cheng | 2019-05-07 |
| 10283625 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2019-05-07 |
| 10262996 | Third type of metal gate stack for CMOS devices | Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman | 2019-04-16 |
| 10242980 | Semiconductor fin isolation by a well trapping fin portion | Henry K. Utomo, Kangguo Cheng, Ravikumar Ramachandran, Huiling Shang, Reinaldo Vega | 2019-03-26 |
| 10229857 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-03-12 |
| 10204836 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-02-12 |
| 10170372 | FINFET CMOS with Si NFET and SiGe PFET | Kangguo Cheng, Jeehwan Kim | 2019-01-01 |
| 10170628 | Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions | Kangguo Cheng | 2019-01-01 |