Issued Patents 2019
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10394116 | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization | Chieh-Yu Lin, Dongbing Shao, Kehan Tian | 2019-08-27 |
| 10395988 | Vertical FET transistor with reduced source/drain contact resistance | Kangguo Cheng, Ruqiang Bao, Zhenxing Bi | 2019-08-27 |
| 10312237 | Vertical transport transistors with equal gate stack thicknesses | Ruqiang Bao, Zhenxing Bi, Choonghyun Lee | 2019-06-04 |
| 10211288 | Vertical transistors with multiple gate lengths | Zhenxing Bi, Kangguo Cheng, Peng Xu | 2019-02-19 |
| 10170640 | FinFET transistor gate and epitaxy formation | Ruqiang Bao, Zhenxing Bi, Kangguo Cheng | 2019-01-01 |