Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8431481 | IC device having low resistance TSV comprising ground connection | Rajiv Dunne, Gary P. Morrison, Satyendra Singh Chauhan, Masood Murtuza | 2013-04-30 |
| 8178976 | IC device having low resistance TSV comprising ground connection | Rajiv Dunne, Gary P. Morrison, Satyendra Singh Chauhan, Masood Murtuza | 2012-05-15 |
| 8154134 | Packaged electronic devices with face-up die having TSV connection to leads and die pad | Gary P. Morrison, Rajiv Dunne, Satyendra Singh Chauhan, Masood Murtuza | 2012-04-10 |
| 8043973 | Mask overhang reduction or elimination after substrate etch | Brian E. Goodlin | 2011-10-25 |
| 7968974 | Scribe seal connection | Scott R. Summerfelt | 2011-06-28 |
| 7960840 | Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level | Thomas W. Winter, William R. Morrison, Gregory D. Winterton, Asad Haider | 2011-06-14 |
| 7833895 | TSVS having chemically exposed TSV tips for integrated circuit devices | Brian E. Goodlin, Mona Eissa | 2010-11-16 |
| 7511350 | Nickel alloy silicide including indium and a method of manufacture therefor | Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Homi Mogul | 2009-03-31 |
| 7402514 | Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer | Robert Tsu, Joe W. McPherson, William R. McKee | 2008-07-22 |
| 7355255 | Nickel silicide including indium and a method of manufacture therefor | Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Homi Mogul | 2008-04-08 |
| 7344985 | Nickel alloy silicide including indium and a method of manufacture therefor | Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Homi Mogul | 2008-03-18 |
| 7211516 | Nickel silicide including indium and a method of manufacture therefor | Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Homi Mogul | 2007-05-01 |
| 7199032 | Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing | Duofeng Yue, Peijun Chen, Sue Crank, Jiong-Ping Lu, Jie Xu | 2007-04-03 |
| 6967349 | Method for fabricating a multi-level integrated circuit having scatterometry test structures stacked over same footprint area | Vladimir A. Ukraintsev | 2005-11-22 |
| 6709974 | Method of preventing seam defects in isolated lines | David Permana, Jiong-Ping Lu, Albert Cheng, Jeff West, Brock W. Fairchild +3 more | 2004-03-23 |
| RE36663 | Planarized selective tungsten metallization system | Gregory C. Smith | 2000-04-18 |
| 5473187 | Hybrids semiconductor circuit | James C. Baker, Emily A. Groves, Douglas E. Paradis, Charles P. Monaghan, Barry Lanier +2 more | 1995-12-05 |
| 5444018 | Metallization process for a semiconductor device | Dennis Yost, Roc Blumenthal | 1995-08-22 |
| 5405807 | Semiconductor hybrids and method of making same | James C. Baker, Emily A. Groves, Douglas E. Paradis, Charles P. Monaghan, Barry Lanier +1 more | 1995-04-11 |
| 5244839 | Semiconductor hybrids and method of making same | James C. Baker, Emily A. Groves, Douglas E. Paradis, Charles P. Monaghan, Barry Lanier +2 more | 1993-09-14 |
| 5055423 | Planarized selective tungsten metallization system | Gregory C. Smith | 1991-10-08 |
| 4891087 | Isolation substrate ring for plasma reactor | Cecil J. Davis, John E. Spencer, Rhett B. Jucha, William J. Stiltz, Randall E. Johnson +2 more | 1990-01-02 |
| 4758305 | Contact etch method | Vic B. Marriott, Rhett B. Jucha, Monte A. Douglas | 1988-07-19 |
| 4654112 | Oxide etch | Monte A. Douglas | 1987-03-31 |
| 4512283 | Plasma reactor sidewall shield | Andrew J. Purdes | 1985-04-23 |