Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12243794 | System in a package modifications | Michael Kenneth Conti, Christopher Lloyd Reinert | 2025-03-04 |
| 12001363 | Secure enclave system-in-package | Peter Robert Linder, Erik James Welsh, William Arthur Fitzhugh LEE | 2024-06-04 |
| 11869823 | System in a package modifications | Michael Kenneth Conti, Christopher Lloyd Reinert | 2024-01-09 |
| 11610844 | High performance module for SiP | Gene A. Frantz, Erik James Welsh, Peter Robert Linder | 2023-03-21 |
| 11502030 | System and method of assembling a system | Erik James Welsh, Peter Robert Linder, Gene A. Frantz | 2022-11-15 |
| 11302648 | EMI shield for molded packages | Peter Robert Linder, Gene A. Frantz | 2022-04-12 |
| 11257803 | System in a package connectors | Erik James Welsh, Christopher Lloyd Reinert, Gene A. Frantz | 2022-02-22 |
| 11211369 | Service module for SIP devices | Gene A. Frantz | 2021-12-28 |
| 11171126 | Configurable substrate and systems | Gene A. Frantz, Neeraj Kumar Reddy Dantu | 2021-11-09 |
| 11157676 | Method for routing bond wires in system in a package (SiP) devices | Neeraj Kumar Reddy Dantu, Gene A. Frantz | 2021-10-26 |
| 10867979 | Circuit mounting structure and lead frame for system in package (SIP) devices | Gene A. Frantz | 2020-12-15 |
| 10714430 | EMI shield for molded packages | Peter Robert Linder, Gene A. Frantz | 2020-07-14 |
| 10204890 | Substrate for system in package (SIP) devices | Gene A. Frantz | 2019-02-12 |
| 9354138 | Fixture for test circuit board reliability testing | Anthony B. Murphy, Guangneng Zhang | 2016-05-31 |
| 8716068 | Method for contacting agglomerate terminals of semiconductor packages | Darvin R. Edwards, Siva Prakash Gurrum, Matthew David Romig, Kazunori Hayata | 2014-05-06 |
| 8643165 | Semiconductor device having agglomerate terminals | Darvin R. Edwards, Siva Prakash Gurrum, Matthew David Romig, Kazunori Hayata | 2014-02-04 |
| 8436475 | IC device having low resistance TSV comprising ground connection | Rajiv Dunne, Gary P. Morrison, Satyendra Singh Chauhan, Thomas D. Bonifield | 2013-05-07 |
| 8431481 | IC device having low resistance TSV comprising ground connection | Rajiv Dunne, Gary P. Morrison, Satyendra Singh Chauhan, Thomas D. Bonifield | 2013-04-30 |
| 8178976 | IC device having low resistance TSV comprising ground connection | Rajiv Dunne, Gary P. Morrison, Satyendra Singh Chauhan, Thomas D. Bonifield | 2012-05-15 |
| 8154134 | Packaged electronic devices with face-up die having TSV connection to leads and die pad | Thomas D. Bonifield, Gary P. Morrison, Rajiv Dunne, Satyendra Singh Chauhan | 2012-04-10 |
| 8039309 | Systems and methods for post-circuitization assembly | Satyendra Singh Chauhan, Donald C. Abbott | 2011-10-18 |
| 8017439 | Dual carrier for joining IC die or wafers to TSV wafers | Yoshimi Takahashi, Rajiv Dunne, Satyendra Singh Chauhan | 2011-09-13 |
| 7915080 | Bonding IC die to TSV wafers | Yoshimi Takahashi, Rajiv Dunne, Satyendra Singh Chauhan | 2011-03-29 |
| 7883936 | Multi layer low cost cavity substrate fabrication for PoP packages | Prema Palaniappan, Satyendra Singh Chauhan | 2011-02-08 |
| 7790597 | Solder cap application process on copper bump using solder powder film | Satyendra Singh Chauhan, Rajiv Dunne, Gary P. Morrison | 2010-09-07 |