Issued Patents All Time
Showing 126–150 of 229 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10734347 | Dummy flip chip bumps for reducing stress | Sheng-Yu Wu, Chita Chuang, Chen-Shien Chen | 2020-08-04 |
| 10734328 | Semiconductor package and manufacturing method thereof | Po-Yuan Teng, Hao-Yi Tsai, Ching-Yao Lin, Teng-Yuan Lo, Chih-Lin Wang | 2020-08-04 |
| 10720416 | Semiconductor package including thermal relaxation block and manufacturing method thereof | Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang | 2020-07-21 |
| 10700008 | Package structure having redistribution layer structures | Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang | 2020-06-30 |
| 10658258 | Chip package and method of forming the same | Kuo Lung Pan, Hao-Yi Tsai | 2020-05-19 |
| 10643943 | Package structure, package-on-package structure and manufacturing method thereof | Chuei-Tang Wang | 2020-05-05 |
| 10522444 | Surface treatment method and apparatus for semiconductor packaging | Chih-Horng Chang, Jie Deng, Ying-Yu Chen | 2019-12-31 |
| 10515919 | Bump-on-trace design for enlarge bump-to-trace distance | Sheng-Yu Wu, Chen-Shien Chen | 2019-12-24 |
| 10510713 | Semicondcutor package and method of manufacturing the same | Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang | 2019-12-17 |
| 10510686 | Semiconductor package and manufacturing method thereof | Po-Yuan Teng, Hao-Yi Tsai, Ching-Yao Lin, Teng-Yuan Lo, Chih-Lin Wang | 2019-12-17 |
| 10504856 | Scheme for connector site spacing and resulting structures | Yu-Feng Chen, Yen-Liang Lin, Sheng-Yu Wu, Chen-Shien Chen | 2019-12-10 |
| 10490468 | Semiconductor structure with conductive structure | Pei-Chun Tsai, Wei Sen Chang, Hao-Yi Tsai | 2019-11-26 |
| 10461023 | Semiconductor packages and methods of forming the same | Mao-Yen Chang, Hao-Yi Tsai, Kuo Lung Pan, Tzung-Hui Lee, Teng-Yuan Lo +1 more | 2019-10-29 |
| 10388622 | Bump structure having a side recess and semiconductor structure including the same | Chih-Horng Chang, Chen-Shien Chen, Yen-Liang Lin | 2019-08-20 |
| 10340236 | Semiconductor device and method of manufacture | Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai | 2019-07-02 |
| 10319691 | Solderless interconnection structure and method of forming same | Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Chen-Shien Chen | 2019-06-11 |
| 10290600 | Dummy flip chip bumps for reducing stress | Sheng-Yu Wu, Chita Chuang, Chen-Shien Chen | 2019-05-14 |
| 10276509 | Integrated fan-out package | Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien Ling Hwang, Wei Sen Chang +1 more | 2019-04-30 |
| 10269759 | Trace design for bump-on-trace (BOT) assembly | Yen-Liang Lin, Chen-Shien Chen | 2019-04-23 |
| 10269674 | Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors | Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai | 2019-04-23 |
| 10269773 | Semiconductor packages and methods of forming the same | Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Hao-Yi Tsai | 2019-04-23 |
| 10163844 | Semiconductor device having conductive bumps of varying heights | Yen-Liang Lin, Sheng-Yu Wu, Chen-Shien Chen | 2018-12-25 |
| 10163801 | Structure and formation method of chip package with fan-out structure | Chih-Horng Chang | 2018-12-25 |
| 10157874 | Contact area design for solder bonding | Pei-Chun Tsai, Yu-Feng Chen, Chen-Shien Chen, Yu-Chih Huang, Sheng-Yu Wu | 2018-12-18 |
| 10153249 | Dual-sided integrated fan-out package | Kuo Lung Pan, Wei Sen Chang, Hao-Yi Tsai, Chung-Shi Liu | 2018-12-11 |