Issued Patents All Time
Showing 576–600 of 694 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8368180 | Scribe line metal structure | Chen-Hua Yu, Hao-Yi Tsai, Shang-Yun Hou, Hsien-Wei Chen, Ming-Yen Chiu | 2013-02-05 |
| 8367474 | Method of manufacturing integrated circuit having stress tuning layer | Clinton Chao, Szu-Wei Lu | 2013-02-05 |
| 8354750 | Stress buffer structures in a mounting structure of a semiconductor device | Tzu-Yu Wang, Tzu-Wei Chiu | 2013-01-15 |
| 8334582 | Protective seal ring for preventing die-saw induced stress | Hsien-Wei Chen, Shang-Yun Hou, Hao-Yi Tsai, Anbiarshy Wu, Yu-Wen Liu | 2012-12-18 |
| 8319349 | Approach for bonding dies onto interposers | Hsien-Pin Hu, Chen-Hua Yu, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou +1 more | 2012-11-27 |
| 8294264 | Radiate under-bump metallization structure for semiconductor devices | Tzu-Yu Wang, Chi-Chun Hsieh, An-Jhih Su, Hsien-Wei Chen, Liwei Lin | 2012-10-23 |
| 8283781 | Semiconductor device having pad structure with stress buffer layer | Wei-Cheng Wu, Shang-Yun Hou, Tzuan-Horng Liu, Tzu-Wei Chiu, Chao-Wen Shih | 2012-10-09 |
| 8278737 | Structure for improving die saw quality | Hsien-Wei Chen, Hao-Yi Tsai, Ying-Ju Chen, Yu-Wen Liu | 2012-10-02 |
| 8237253 | Package structures | Benson Liu, Hsien-Wei Chen, Hao-Yi Tsai | 2012-08-07 |
| 8227916 | Package structure and method for reducing dielectric layer delamination | Hsiu-Ping Wei, Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen +1 more | 2012-07-24 |
| 8227917 | Bond pad design for fine pitch wire bonding | Shih-Hsun Hsu, Hao-Yi Tsai, Benson Liu, Chia-Lun Tsai, Hsien-Wei Chen +2 more | 2012-07-24 |
| 8203209 | Bond pad design for reducing the effect of package stress | Chen-Hua Yu, Hao-Yi Tsai, Hsien-Wei Chen | 2012-06-19 |
| 8193639 | Dummy metal design for packaging structures | Tzuan-Horng Liu, Shang-Yun Hou, Wei-Cheng Wu, Hsiu-Ping Wei, Chih-Hua Chen +3 more | 2012-06-05 |
| 8178980 | Bond pad structure | Yu-Wen Liu, Hao-Yi Tsai, Hsien-Wei Chen | 2012-05-15 |
| 8174124 | Dummy pattern in wafer backside routing | Ming-Yen Chiu, Hsien-Wei Chen, Ming-Fa Chen | 2012-05-08 |
| 8169076 | Interconnect structures having lead-free solder bumps | Mirng-Ji Lii, Chien-Hsiun Lee, Chen-Hua Yu, Chin-Yu Ku | 2012-05-01 |
| 8125233 | Parametric testline with increased test pattern areas | Hsien-Wei Chen, Shih-Hsun Hsu, Hao-Yi Tsai | 2012-02-28 |
| 8125052 | Seal ring structure with improved cracking protection | Shih-Hsun Hsu, Shang-Yun Hou, Hao-Yi Tsai, Chen-Hua Yu | 2012-02-28 |
| 8105875 | Approach for bonding dies onto interposers | Hsien-Pin Hu, Chen-Hua Yu, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou +1 more | 2012-01-31 |
| 8058151 | Methods of die sawing | Hao-Yi Tsai | 2011-11-15 |
| 8030776 | Integrated circuit with protective structure | Chen-Hua Yu, Shang-Yun Hou, Hao-Yi Tsai, Hsien-Wei Chen, Hsiu-Ping Wei | 2011-10-04 |
| 8013333 | Semiconductor test pad structures | Hsien-Wei Chen, Ying-Ju Chen, Yu-Wen Liu, Hao-Yi Tsai | 2011-09-06 |
| 7994046 | Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the air gap | — | 2011-08-09 |
| 7952453 | Structure design for minimizing on-chip interconnect inductance | Hsien-Wei Chen, Hsueh-Chung Chen | 2011-05-31 |
| 7952167 | Scribe line layout design | Hsin-Hui Lee, Mirng-Ji Lii, Shang-Yun Hou | 2011-05-31 |