Issued Patents All Time
Showing 226–248 of 248 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8504972 | Standard cells having flexible layout architecture/boundaries | Yung-Chin Hou, David B. Scott, Lee-Chung Lu | 2013-08-06 |
| 8482990 | Memory edge cell | Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Cheng Hung Lee +1 more | 2013-07-09 |
| 8473888 | Systems and methods of designing integrated circuits | Ta-Pen Guo, Shyue-Shyh Lin, Mei-Hui Huang | 2013-06-25 |
| 8455354 | Layouts of POLY cut openings overlapping active regions | Jung-Hsuan Chen, Yen-Huei Chen, Hung-Jen Liao | 2013-06-04 |
| 8431985 | Layout and process of forming contact plugs | Yung-Chin Hou, Lee-Chung Lu, Shyue-Shyh Lin | 2013-04-30 |
| 8418111 | Method and apparatus for achieving multiple patterning technology compliant design layout | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Lee-Chung Lu, Ru-Gun Liu +3 more | 2013-04-09 |
| 8365102 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Ru-Gun Liu, Lee-Chung Lu | 2013-01-29 |
| 8356262 | Cell architecture and method | Lee-Chung Lu, Shyue-Shyh Lin, Zhe-Wei Jiang | 2013-01-15 |
| 8255837 | Methods for cell boundary isolation in double patterning design | Lee-Chung Lu, Yi-Kan Cheng, Yuan-Te Hou, Yung-Chin Hou | 2012-08-28 |
| 8217469 | Contact implement structure for high density design | Yung-Chin Hou, Yuh-Jier Mii, Kuo-Tung Sung | 2012-07-10 |
| 7966596 | Place-and-route layout method with same footprint cells | Lee-Chung Lu, Chung-Hsing Wang, Ping Li, Chun-Hui Tai, Gwan Sin Chang | 2011-06-21 |
| 7932566 | Structure and system of mixing poly pitch cell design under default poly pitch design rules | Yung-Chin Hou, Lee-Chung Lu, Ping Li, Ta-Pen Guo | 2011-04-26 |
| 7821039 | Layout architecture for improving circuit performance | Lee-Chung Lu, Yung-Chin Hou, Chun-Hui Tai, Ta-Pen Guo, Sheng-Hsin Chen +1 more | 2010-10-26 |
| 7808051 | Standard cell without OD space effect in Y-direction | Yung-Chin Hou, Lee-Chung Lu, Ta-Pen Guo, Ping Li, Chun-Hui Tai +1 more | 2010-10-05 |
| 7496862 | Method for automatically modifying integrated circuit layout | Mi-Chang Chang, Su-Ya Lin, Jen-Hang Yang | 2009-02-24 |
| 7458051 | ECO cell for reducing leakage power | Yung-Chin Hou, Lee-Chung Lu, Chu-Ping Wang | 2008-11-25 |
| 7321139 | Transistor layout for standard cell with optimized mechanical stress effect | Mi-Chang Chang, Liang Han, Huan-Tsung Huang, Wen-Jya Liang | 2008-01-22 |
| 7247894 | Very fine-grain voltage island integrated circuit | Cliff Hou, Ching-Hao Shaw, Wan-Pin Yu, Chia-Lin Cheng, Lee-Chung Lu | 2007-07-24 |
| 7137094 | Method for reducing layers revision in engineering change order | — | 2006-11-14 |
| 6973636 | Method of defining forbidden pitches for a lithography exposure tool | Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Burn Jeng Lin, Mi-Chang Chang +4 more | 2005-12-06 |
| 6903389 | Variable layout design for multiple voltage applications | Chun-Hui Tai | 2005-06-07 |
| 6849904 | Efficient source diffusion interconnect, MOS transistor and standard cell layout utilizing same | Ching-Hao Shaw | 2005-02-01 |
| 6477696 | Routing definition to optimize layout design of standard cells | — | 2002-11-05 |