HH

Huan-Tsung Huang

TSMC: 17 patents #1,893 of 12,232Top 20%
PS Pdf Solutions: 1 patents #76 of 143Top 55%
📍 Baoshan, CA: #15 of 69 inventorsTop 25%
Overall (All Time): #251,305 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDate
11621351 Epi block structure in semiconductor product providing high breakdown voltage Chia-Hsin Hu 2023-04-04
10998443 Epi block structure in semiconductor product providing high breakdown voltage Chia-Hsin Hu 2021-05-04
10679723 Direct memory characterization using periphery transistors Dong-Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky +1 more 2020-06-09
9812444 Fin-type resistor Chia-Hsin Hu, Hsueh-Shih Fan 2017-11-07
9691758 Fin-type resistor Chia-Hsin Hu, Hsueh-Shih Fan 2017-06-27
9443925 Semiconductor structure with dielectric-sealed doped region Kuo-Cheng Wu, Carlos H. Diaz 2016-09-13
9136329 Semiconductor structure with dielectric-sealed doped region Kuo-Cheng Wu, Carlos H. Diaz 2015-09-15
8754487 Semiconductor device with metal gate Yuri Masuoka 2014-06-17
8679926 Local charge and work function engineering on MOSFET Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto 2014-03-25
8415749 Semiconductor structure with dielectric-sealed doped region Kou-Cheng Wu, Carlos H. Diaz 2013-04-09
8357581 Transistor performance improving method with metal gate Yuri Masuoka 2013-01-22
8324090 Method to improve dielectric quality in high-k metal gate technology Yuri Masuoka, Peng-Fu Hsu, Kuo-Tai Huang, Yong-Tian Hou, Carlos H. Diaz 2012-12-04
8030718 Local charge and work function engineering on MOSFET Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto 2011-10-04
8012817 Transistor performance improving method with metal gate Yuri Masuoka 2011-09-06
7768072 Silicided metal gate for multi-threshold voltage configuration Ching-Wei Tsai, Chih-Hao Wang, Wei-Jung Lin, Carlos H. Diaz 2010-08-03
7759210 Method for forming a MOS device with reduced transient enhanced diffusion Fung Ka Hing 2010-07-20
7321139 Transistor layout for standard cell with optimized mechanical stress effect Mi-Chang Chang, Liang Han, Wen-Jya Liang, Li-Chun Tien 2008-01-22
6960512 Method for manufacturing a semiconductor device having an improved disposable spacer Shui-Ming Cheng, Ka-Hing Fung, Yin-Pin Wang, Kuan-Lun Cheng 2005-11-01