Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11004950 | Integrated circuit metal gate structure | Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung | 2021-05-11 |
| 10164045 | Integrated circuit metal gate structure | Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung | 2018-12-25 |
| 9397184 | Semiconductor device having metal gate and manufacturing method thereof | — | 2016-07-19 |
| 9309570 | Method and device for genetic map construction, method and device for haplotype analysis | Luting Song, Di Shao, Zequn Zheng, Zhijun Zheng, Kui Wu +2 more | 2016-04-12 |
| 8836038 | CMOS dual metal gate semiconductor device | Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee | 2014-09-16 |
| 8679962 | Integrated circuit metal gate structure and method of fabrication | Chien-Hao Chen, Donald Y. Chao, Cheng-Lung Hung | 2014-03-25 |
| 8536660 | Hybrid process for forming metal gates of MOS devices | Peng-Fu Hsu, Ssu-Yi Li, Kuo-Tai Huang, Mong-Song Liang | 2013-09-17 |
| 8384159 | Semiconductor devices and methods with bilayer dielectrics | Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent Chang, Jin Ying +1 more | 2013-02-26 |
| 8324090 | Method to improve dielectric quality in high-k metal gate technology | Yuri Masuoka, Peng-Fu Hsu, Huan-Tsung Huang, Kuo-Tai Huang, Carlos H. Diaz | 2012-12-04 |
| 8258546 | High-k metal gate device | Cheng-Lung Hung, Keh-Chiang Ku, Chien-Hao Huang | 2012-09-04 |
| 7994051 | Implantation method for reducing threshold voltage for high-K metal gate device | Cheng-Lung Hung, Keh-Chiang Ku, Chien-Hao Huang | 2011-08-09 |
| 7989321 | Semiconductor device gate structure including a gettering layer | Chien-Hao Chen, Peng-Fu Hsu, Kuo-Tai Huang, Donald Y. Chao, Cheng-Lung Hung | 2011-08-02 |
| 7871915 | Method for forming metal gates in a gate last process | Peng-Soon Lim, Chien-Hao Chen, Chi-Chun Chen | 2011-01-18 |
| 7812414 | Hybrid process for forming metal gates | Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee | 2010-10-12 |
| 7531399 | Semiconductor devices and methods with bilayer dielectrics | Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent Chang, Jin Ying +1 more | 2009-05-12 |
| 7465634 | Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures | Peng-Soon Lim, Jin Ying, Hun-Jan Tao | 2008-12-16 |
| 7002175 | Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration | Jagar Singh, Ming Li | 2006-02-21 |