Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9698185 | Partial buried channel transfer device for image sensors | Gang Chen, Sing-Chung Hu, Hsin-Chih Tai, Duli Mao, Manoj Bikumandla +5 more | 2017-07-04 |
| 8804021 | Method, apparatus and system for providing improved full well capacity in an image sensor pixel | Sohei Manabe, Vincent Venezia, Hsin-Chih Tai, Duli Mao, Howard E. Rhodes | 2014-08-12 |
| 8729655 | Etching narrow, tall dielectric isolation structures from a dielectric layer | Chia-Ying Liu, Wu-Zhang Yang | 2014-05-20 |
| 8729712 | Pad design for circuit under pad in semiconductor devices | Yin Qian, Dyson H. Tai, Vincent Venezia, Duli Mao, Wei Zheng +1 more | 2014-05-20 |
| 8614112 | Method of damage-free impurity doping for CMOS image sensors | Chia-Ying Liu, Hsin-Chih Tai, Vincent Venezia | 2013-12-24 |
| 8569856 | Pad design for circuit under pad in semiconductor devices | Yin Qian, Hsin-Chih Tai, Vincent Venezia, Duli Mao, Wei Zheng +1 more | 2013-10-29 |
| 8471316 | Isolation area between semiconductor devices having additional active area | Hsin-Chih Tai, Duli Mao, Vincent Venezia, Gang Chen | 2013-06-25 |
| 8466010 | Seal ring support for backside illuminated image sensor | Hsin-Chih Tai, Vincent Venezia, Yin Qian, Duli Mao | 2013-06-18 |
| 8373243 | Seal ring support for backside illuminated image sensor | Hsin-Chih Tai, Vincent Venezia, Yin Qian, Duli Mao | 2013-02-12 |
| 8349732 | Implanted metal silicide for semiconductor device | Harry-Hak-Lay Chuang, Hung-Chih Tsai, Kong-Beng Thei, Mong-Song Liang | 2013-01-08 |
| 8338263 | Etching narrow, tall dielectric isolation structures from a dielectric layer | Chia-Ying Liu, Wu-Zhang Yang | 2012-12-25 |
| 8258546 | High-k metal gate device | Cheng-Lung Hung, Yong-Tian Hou, Chien-Hao Huang | 2012-09-04 |
| 8212253 | Shallow junction formation and high dopant activation rate of MOS devices | Chun-Feng Nieh, Nai-Han Cheng, Chi-Chun Chen, Li-Te Lin | 2012-07-03 |
| 8071429 | Wafer dicing using scribe line etch | Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Wei Zheng +1 more | 2011-12-06 |
| 8058134 | Junction profile engineering using staged thermal annealing | Li-Ting Wang, Yu-Chang Lin, Nai-Han Cheng, Li-Ping Huang | 2011-11-15 |
| 8039375 | Shallow junction formation and high dopant activation rate of MOS devices | Chun-Feng Nieh, Nai-Han Cheng, Chi-Chun Chen, Li-Te Lin | 2011-10-18 |
| 7994051 | Implantation method for reducing threshold voltage for high-K metal gate device | Cheng-Lung Hung, Yong-Tian Hou, Chien-Hao Huang | 2011-08-09 |
| 7741699 | Semiconductor device having ultra-shallow and highly activated source/drain extensions | Chun-Feng Nieh, Li-Ping Huang, Chih-Chiang Wang, Chien-Hao Chen, Hsun Chang +3 more | 2010-06-22 |
| 7736968 | Reducing poly-depletion through co-implanting carbon and nitrogen | Cheng-Lung Hung, Li-Ting Wang, Chien-Hao Chen, Chien-Hao Huang, Wenli Lin +1 more | 2010-06-15 |
| 7504292 | Short channel effect engineering in MOS device using epitaxially carbon-doped silicon | Pang-Yen Tsai, Chun-Feng Nieh, Li-Ting Wang | 2009-03-17 |
| 7494857 | Advanced activation approach for MOS devices | Chien-Hao Chen, Tze-Liang Lee, Shih-Chang Chen, Chun-Feng Nieh, Li-Ting Wang +1 more | 2009-02-24 |
| 7482211 | Junction leakage reduction in SiGe process by implantation | Chun-Feng Nieh, Chien-Hao Chen, Tze-Liang Lee, Shih-Chang Chen | 2009-01-27 |