Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9366969 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | Chia-Chu Liu, Kuei-Shun Chen, Norman Chen, Chin-Hsiang Lin | 2016-06-14 |
| 9091923 | Contrast enhancing exposure system and method for use in semiconductor fabrication | George Liu, Norman Chen, Kuei-Shun Chen, Chin-Hsiang Lin | 2015-07-28 |
| 8815496 | Method for patterning a photosensitive layer | Hsiao-Tzu Lu, Kuei-Shun Chen, Tsiao-Chen Wu, George Liu | 2014-08-26 |
| 8623231 | Method for etching an ultra thin film | George Liu, Kuei-Shun Chen, Chih-Yang Yeh | 2014-01-07 |
| 8472005 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | George Liu, Kuei-Shun Chen, Norman Chen, Chin-Hsiang Lin | 2013-06-25 |
| 8394576 | Method for patterning a photosensitive layer | Hsiao-Tzu Lu, Kuei-Shun Chen, Tsiao-Chen Wu, George Liu | 2013-03-12 |
| 8384159 | Semiconductor devices and methods with bilayer dielectrics | Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Yong-Tian Hou, Jin Ying +1 more | 2013-02-26 |
| 8124323 | Method for patterning a photosensitive layer | Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, George Liu | 2012-02-28 |
| 8119533 | Pattern formation in semiconductor fabrication | George Liu, Kuei-Shun Chen, Shang-Wen Chang | 2012-02-21 |
| 7960821 | Dummy vias for damascene process | Kuei-Shun Chen, Chin-Hsiang Lin, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen | 2011-06-14 |
| 7767570 | Dummy vias for damascene process | Kuei-Shun Chen, Chin-Hsiang Lin, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen | 2010-08-03 |
| 7648918 | Method of pattern formation in semiconductor fabrication | George Liu, Kuei-Shun Chen, Shang-Wen Chang | 2010-01-19 |
| 7642101 | Semiconductor device having in-chip critical dimension and focus patterns | George Liu, Chin-Hsiang Lin, Kuei-Shun Chen, Norman Chen | 2010-01-05 |
| 7531399 | Semiconductor devices and methods with bilayer dielectrics | Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Yong-Tian Hou, Jin Ying +1 more | 2009-05-12 |
| 7432042 | Immersion lithography process and mask layer structure applied in the same | George Liu, Norman Chen | 2008-10-07 |
| 7387969 | Top patterned hardmask and method for patterning | George Liu, Norman Chen, Yao-Ching Ku, Chin-Hsiang Lin, Kuei-Shun Chen | 2008-06-17 |
| 6844143 | Sandwich photoresist structure in photolithographic process | Benjamin Szu-Min Lin, George Liu, Cheng-Chung Chen | 2005-01-18 |
| 6680252 | Method for planarizing barc layer in dual damascene process | Anseime Chen, Hui Huang, Andersen Chang | 2004-01-20 |
| 6458705 | Method for forming via-first dual damascene interconnect structure | Kuei-Chun Hung, I-Hsiung Huang, Ya Hui Chang | 2002-10-01 |