LL

Lawrence Lin

TSMC: 3 patents #5,465 of 12,232Top 45%
UM United Microelectronics: 3 patents #1,523 of 4,560Top 35%
MM Monolithic Memories: 1 patents #17 of 45Top 40%
MT Monsanto Technology: 1 patents #877 of 1,657Top 55%
📍 Chesterfield, MO: #799 of 6,461 inventorsTop 15%
🗺 Missouri: #2,677 of 23,789 inventorsTop 15%
Overall (All Time): #655,653 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
7960821 Dummy vias for damascene process Kuei-Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lai Chien Wen, Jhun Hua Chen 2011-06-14
7767570 Dummy vias for damascene process Kuei-Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lai Chien Wen, Jhun Hua Chen 2010-08-03
7226873 Method of improving via filling uniformity in isolated and dense via-pattern regions Yung-Sung Yen, Kuei-Shun Chen, Chia-Hsiang Lin, Tsung-Hsien Lin 2007-06-05
6833318 Gap-filling process Chun-Jen Weng, Juan-Yi Chen, Hong-Tsz Pan, Cedric Lee, Der-Yuan Wu +3 more 2004-12-21
5565376 Device isolation technology by liquid phase deposition Water Lur 1996-10-15
5449638 Process on thickness control for silicon-on-insulator technology Gary Hong, Chen-Chiu Hsue, H. J. Wu 1995-09-12
4721682 Isolation and substrate connection for a bipolar integrated circuit Scott O. Graham, Hua-Thye Chua 1988-01-26
4228578 Method for off-orientation point rotation sawing of crystalline rod material Henry W. Gutsche, James Collier 1980-10-21