Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11482517 | Integrated circuit | En-Chiuan Liou, Chih-Wei Yang | 2022-10-25 |
| 9905562 | Semiconductor integrated circuit layout structure | Shih-Chin Lin, Jerry Hu, Ming-Jui Chen, Chen-Hsien Hsu | 2018-02-27 |
| 9673145 | Semiconductor integrated circuit layout structure | Shih-Chin Lin, Jerry Hu, Ming-Jui Chen, Chen-Hsien Hsu | 2017-06-06 |
| 9653346 | Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch | Shih-Chin Lin, Jerry Hu, Ming-Jui Chen, Chen-Hsien Hsu | 2017-05-16 |
| 9524362 | Method of decomposing layout for generating patterns on photomasks | Harn-Jiunn Wang, Chih-Hsien Tang, Chin-Lung Lin | 2016-12-20 |
| 9007571 | Measurement method of overlay mark | Wei-Jhe Tzai, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin | 2015-04-14 |
| 7101796 | Method for forming a plane structure | Jui-Tsen Huang | 2006-09-05 |
| 6839126 | Photolithography process with multiple exposures | Yeong-Song Yen, I-Hsiung Huang, Jiunn-Ren Hwang, Ching-Hsu Chang | 2005-01-04 |
| 6638664 | Optical mask correction method | Chang-Jyh Hsieh, Jiunn-Ren Hwang, Chien-Ming Wang | 2003-10-28 |
| 6624055 | Method for forming a plane structure | Jui-Tsen Huang | 2003-09-23 |
| 6589881 | Method of forming dual damascene structure | I-Hsiung Huang, Jiunn-Ren Hwang, Ching-Hsu Chang | 2003-07-08 |
| 6458705 | Method for forming via-first dual damascene interconnect structure | Vencent Chang, I-Hsiung Huang, Ya Hui Chang | 2002-10-01 |
| 6337269 | Method of fabricating a dual damascene structure | I-Hsiung Huang, Jiunn-Ren Hwang | 2002-01-08 |