Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12408393 | Semiconductor device with a single diffusion break structure and a gate structure having aligned sidewalls | Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng | 2025-09-02 |
| 12278265 | Method for fabricating a fin with minimal length between two single-diffusion break (SDB) trenches | Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng | 2025-04-15 |
| 11715759 | Semiconductor device with a single diffusion break structure having a sidewall aligned with a gate sidewall | Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng | 2023-08-01 |
| 10153034 | Static random access memory unit structure | Tan-Ya Yin, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang | 2018-12-11 |
| 9905562 | Semiconductor integrated circuit layout structure | Shih-Chin Lin, Kuei-Chun Hung, Jerry Hu, Chen-Hsien Hsu | 2018-02-27 |
| 9859170 | Method of forming semiconductor structure | Ching-Wen Hung, Wei-Cyuan Lo, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee +8 more | 2018-01-02 |
| 9785046 | Pattern verifying method | Te-Hsien Hsieh, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen | 2017-10-10 |
| 9747404 | Method for optimizing an integrated circuit layout design | Shih-Ming Kuo, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen | 2017-08-29 |
| 9673145 | Semiconductor integrated circuit layout structure | Shih-Chin Lin, Kuei-Chun Hung, Jerry Hu, Chen-Hsien Hsu | 2017-06-06 |
| 9653346 | Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch | Shih-Chin Lin, Kuei-Chun Hung, Jerry Hu, Chen-Hsien Hsu | 2017-05-16 |
| 9627036 | Static random access memory layout structure | Tan-Ya Yin, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang | 2017-04-18 |
| 9613969 | Semiconductor structure and method of forming the same | Ching-Wen Hung, Wei-Cyuan Lo, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee +8 more | 2017-04-04 |
| 9524361 | Method for decomposing a layout of an integrated circuit | Ting-Cheng Tseng, Chia-Wei Huang | 2016-12-20 |
| 9368365 | Method for forming a semiconductor structure | Shih-Hsun Kuo, Ting-Cheng Tseng, Tan-Ya Yin, Chia-Wei Huang | 2016-06-14 |
| 9274416 | Method for forming photo-mask and OPC method | Chun-Hsien Huang, Chia-Wei Huang, Hsin-Yu Chen, Kai-Lin Chuang | 2016-03-01 |
| 9262820 | Method and apparatus for integrated circuit design | Te-Hsien Hsieh, Cheng-Te Wang, Jing-Yi Lee | 2016-02-16 |
| 9208276 | Method for generating layout pattern | Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Shih-Fang Tzou, Ming-Te Wei | 2015-12-08 |
| 9141744 | Method for generating layout pattern | Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Shih-Fang Tzou, Ming-Te Wei | 2015-09-22 |
| 9104833 | Mask set for double exposure process and method of using the mask set | Hui-Fang Kuo, Ting-Cheng Tseng, Cheng-Te Wang | 2015-08-11 |
| 9047658 | Method of optical proximity correction | Te-Hsien Hsieh, Cheng-Te Wang, Ping-I Hsieh, Jing-Yi Lee | 2015-06-02 |
| 8966410 | Semiconductor structure and method for fabricating semiconductor layout | Chia-Wei Huang, Chun-Hsien Huang | 2015-02-24 |
| 8930858 | Method for optical proximity correction | Hui-Fang Kuo | 2015-01-06 |
| 8885917 | Mask pattern and correcting method thereof | Te-Hsien Hsieh, Cheng-Te Wang, Jing-Yi Lee | 2014-11-11 |
| 8822328 | Method for patterning semiconductor structure | Chia-Wei Huang, Ting-Cheng Tseng, Ping-I Hsieh | 2014-09-02 |
| 8810785 | Mask inspecting method | Wei-Cyuan Lo, Yung-Feng Cheng | 2014-08-19 |