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Via landing on first and second barrier layers to reduce cleaning time of conductive structure |
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3D RRAM cell structure for reducing forming and set voltages |
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High density memory devices with low cell leakage and methods for forming the same |
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Ion beam etching chamber with etching by-product redistributor |
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2022-02-01 |
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3D RRAM cell structure for reducing forming and set voltages |
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2021-08-10 |
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Pattern verifying method |
Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen |
2017-10-10 |
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Method for optimizing an integrated circuit layout design |
Shih-Ming Kuo, Ming-Jui Chen, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen |
2017-08-29 |
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Method and apparatus for integrated circuit design |
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2016-02-16 |
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Method of optical proximity correction |
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2015-06-02 |
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Mask pattern and correcting method thereof |
Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee |
2014-11-11 |
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Method of optical proximity correction according to complexity of mask pattern |
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2014-08-12 |
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Method for making photomask layout |
Shih-Ming Kuo, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee |
2014-06-03 |
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Double patterning mask set and method of forming thereof |
Ming-Jui Chen, Shih-Ming Kuo, Ping-I Hsieh, Cheng-Te Wang, Jing-Yi Lee |
2013-02-26 |
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Optical proximity correction process |
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