Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8772056 | Dummy pattern design for thermal annealing | Li-Ting Wang | 2014-07-08 |
| 8653576 | Method of fabricating a SONOS gate structure with dual-thickness oxide | Tzyh-Cheang Lee, Tsung-Lin Lee | 2014-02-18 |
| 8618610 | Dummy pattern design for thermal annealing | Li-Ting Wang | 2013-12-31 |
| 8173990 | Memory array with a selector connected to multiple resistive cells | Tzyh-Cheang Lee, Chun-Sheng Liang, Fu-Liang Yang | 2012-05-08 |
| 7847335 | Non-volatile memory device having a generally L-shaped cross-section sidewall SONOS | Tzyh-Cheang Lee, Tsung-Lin Lee | 2010-12-07 |
| 7714376 | Non-volatile memory device with polysilicon spacer and method of forming the same | Tzyh-Cheang Lee, Tsung-Lin Lee | 2010-05-11 |
| 7663134 | Memory array with a selector connected to multiple resistive cells | Tzyh-Cheang Lee, Chun-Sheng Liang, Fu-Liang Yang | 2010-02-16 |
| 7589387 | SONOS type two-bit FinFET flash memory cell | Min-hwa Chi, Fu-Liang Yang | 2009-09-15 |
| 7482231 | Manufacturing of memory array and periphery | Tzyh-Cheang Lee, Fu-Liang Yang, Tsung-Lin Lee | 2009-01-27 |
| 7482236 | Structure and method for a sidewall SONOS memory device | Tzyh-Cheang Lee, Fu-Liang Yang, Tsung-Lin Lee | 2009-01-27 |
| 7405119 | Structure and method for a sidewall SONOS memory device | Tzyh-Cheang Lee, Fu-Liang Yang, Tsung-Lin Lee | 2008-07-29 |
| 7355236 | Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof | Tzyh-Cheang Lee, Fu-Liang Yang, Tsung-Lin Lee | 2008-04-08 |
| 7326622 | Method of manufacturing semiconductor MOS transistor device | Yi-Cheng Liu, Wei-Tsun Shiau, Cheng-Tung Huang, Kuan-Yang Liao | 2008-02-05 |
| 7297450 | Optical proximity correction method | Jui-Tsen Huang, Chang-Jyh Hsieh | 2007-11-20 |
| 7186657 | Method for patterning HfO2-containing dielectric | Jeng H. Hwang, Wei-Tsun Shiau, Chien-Ting Lin | 2007-03-06 |
| 7176084 | Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory | Tzyh-Cheang Lee, Fu-Liang Yang, Tsung-Lin Lee | 2007-02-13 |
| 7063923 | Optical proximity correction method | Jui-Tsen Huang, Chang-Jyh Hsieh | 2006-06-20 |
| 6974650 | Method of correcting a mask layout | Kay-Ming Lee, Cheng-Wen Fan, Chih-Chiang Liu | 2005-12-13 |
| 6853031 | Structure of a trapezoid-triple-gate FET | Wen-Shiang Liao, Wei-Tsun Shiau | 2005-02-08 |
| 6839126 | Photolithography process with multiple exposures | Yeong-Song Yen, I-Hsiung Huang, Kuei-Chun Hung, Ching-Hsu Chang | 2005-01-04 |
| 6767679 | Correcting the polygon feature pattern with an optical proximity correction method | Chang-Jyh Hsieh, Jui-Tsen Huang | 2004-07-27 |
| 6680163 | Method of forming opening in wafer layer | I-Hsiung Huang | 2004-01-20 |
| 6664028 | Method of forming opening in wafer layer | I-Hsiung Huang | 2003-12-16 |
| 6656667 | Multiple resist layer photolithographic process | I-Hsiung Huang | 2003-12-02 |
| 6638664 | Optical mask correction method | Chang-Jyh Hsieh, Kuei-Chun Hung, Chien-Ming Wang | 2003-10-28 |