Issued Patents All Time
Showing 176–200 of 248 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9653393 | Method and layout of an integrated circuit | Wei-Yu Chen, Hui-Zhong Zhuang, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-05-16 |
| 9626472 | Method and system of forming layout design | Ting-Wei Chiang, Hui-Zhong Zhuang, Zhe-Wei Jiang | 2017-04-18 |
| 9608604 | Voltage level shifter with single well voltage | Lee-Chung Lu, Chung-Hsing Wang, Chun-Hui Tai, Shun Li Chen | 2017-03-28 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Ru-Gun Liu, Lee-Chung Lu | 2017-03-14 |
| 9563731 | Cell boundaries for self aligned multiple patterning abutments | Chin-Hsiung Hsu, Pin-Dai Sue, Ching-Hsiang Chang, Wen-Hao Chen, Cheng-I Huang | 2017-02-07 |
| 9543193 | Non-hierarchical metal layers for integrated circuits | Lee-Chung Lu, Yuan-Te Hou, Shyue-Shyh Lin, Dian-Hau Chen | 2017-01-10 |
| 9536032 | Method and system of layout placement based on multilayer gridlines | Ting-Wei Chiang, Hui-Zhong Zhuang, Zhe-Wei Jiang | 2017-01-03 |
| 9529955 | Integrated circuit layout | Chan-Hong Chern, Fu-Lung Hsueh | 2016-12-27 |
| 9478533 | Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration | Wei Ma, Bo-Ting Chen, Ting Yu Chen, Kuo-Ji Chen | 2016-10-25 |
| 9478609 | Integrated circuit with multiple cells having different heights | Ting-Wei Chiang, Ming Jin Huang, Pin-Dai Sue | 2016-10-25 |
| 9478540 | Adaptive fin design for FinFETs | Tsong-Hua Ou, Shu-Min Chen, Pin-Dai Sue, Ru-Gun Liu | 2016-10-25 |
| 9443758 | Connecting techniques for stacked CMOS devices | Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang | 2016-09-13 |
| 9431381 | System and method of processing cutting layout and example switching circuit | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang | 2016-08-30 |
| 9425141 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang | 2016-08-23 |
| 9425095 | Distributed metal routing | You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao | 2016-08-23 |
| 9412700 | Semiconductor device and method of manufacturing semiconductor device | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang | 2016-08-09 |
| 9406815 | Adding decoupling function for TAP cells | Kuo-Ji Chen | 2016-08-02 |
| 9401258 | Fuse structure | Chen-Ming Hung, Yun-Han Chen, Shao-Tung Peng, Shao-Yu Chou, Yue-Der Chih | 2016-07-26 |
| 9337290 | Layout architecture for performance improvement | Lee-Chung Lu, Hui-Zhong Zhuang | 2016-05-10 |
| 9336348 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang +1 more | 2016-05-10 |
| 9323881 | Method and layout of an integrated circuit | Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ruei-Wun SUN, Hung-Jung Tseng +1 more | 2016-04-26 |
| 9317646 | Masks formed based on integrated circuit layout design having cell that includes extended active region | Lee-Chung Lu, Hui-Zhong Zhuang, Chang-Yu Wu | 2016-04-19 |
| 9312260 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Ta-Pen Guo, Helen Shu-Hui Chang, Hsiang-Jen Tseng, Shyue-Shyh Lin +6 more | 2016-04-12 |
| 9287276 | Memory cell array | Shi-Wei Chang, Hong-Chen Cheng, Chien-Chi TIEN, Kuo-Hua Pan, Jhon Jhy Liaw | 2016-03-15 |
| 9245887 | Method and layout of an integrated circuit | Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang +1 more | 2016-01-26 |