Issued Patents All Time
Showing 151–175 of 248 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10325900 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2019-06-18 |
| 10296694 | Integrated circuit and method of manufacturing same | Ting-Wei Chiang, Hui-Zhong Zhuang | 2019-05-21 |
| 10277227 | Semiconductor device layout | Pin-Dai Sue, Ting-Wei Chiang, Hui-Zhong Zhuang, Shun Li Chen | 2019-04-30 |
| 10269784 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2019-04-23 |
| 10270430 | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same | Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang Jui Kao, Lee-Chung Lu | 2019-04-23 |
| 10268796 | Method and system for pin layout | Fong-Yuan Chang, Shun Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang | 2019-04-23 |
| 10163880 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2018-12-25 |
| 10157910 | Circuits and structures including tap cells and fabrication methods thereof | Jin Xu, Ting-Wei Chiang, Hui-Zhong Zhuang | 2018-12-18 |
| 10157902 | Semiconductor devices with cells comprising routing resources | Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Chi-Yu Lu | 2018-12-18 |
| 10157840 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Po-Hsiang Huang +6 more | 2018-12-18 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2018-11-27 |
| 10127340 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Chi-Yu Lu | 2018-11-13 |
| 10007750 | Gate pad layout patterns for masks and structures | Ting-Wei Chiang, Shun Li Chen, Yi-Hsun Chiu | 2018-06-26 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang +1 more | 2018-06-05 |
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang +1 more | 2018-02-20 |
| 9853008 | Connecting techniques for stacked CMOS devices | Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang | 2017-12-26 |
| 9846757 | Cell grid architecture for FinFET technology | Hui-Zhong Zhuang, Ting-Wei Chiang, Chung-Te Lin | 2017-12-19 |
| 9846755 | Method for cell placement in semiconductor layout and system thereof | Ming-Zhang Kuo, Lee-Chung Lu, Cheng-Chung Lin, Sang Hoo Dhong, Ta-Pen Guo | 2017-12-19 |
| 9831230 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-11-28 |
| 9806071 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang | 2017-10-31 |
| 9767243 | System and method of layout design for integrated circuits | Ting-Wei Chiang, Hui-Zhong Zhuang | 2017-09-19 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang +2 more | 2017-08-29 |
| 9691750 | Semiconductor device and layout method thereof | Ting Wei Chou, WEN-LANG WU, Chitong Chen, Shun Li Chen, Ting-Wei Chiang | 2017-06-27 |
| 9690892 | Masks based on gate pad layout patterns of standard cell having different gate pad pitches | Ting-Wei Chiang, Shun Li Chen, Yi-Hsun Chiu | 2017-06-27 |
| 9691666 | Layout architecture for performance improvement | Lee-Chung Lu, Hui-Zhong Zhuang | 2017-06-27 |