Issued Patents All Time
Showing 201–225 of 248 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9213795 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang +2 more | 2015-12-15 |
| 9123565 | Masks formed based on integrated circuit layout design having standard cell that includes extended active region | Lee-Chung Lu, Hui-Zhong Zhuang, Chang-Yu Wu | 2015-09-01 |
| 9117882 | Non-hierarchical metal layers for integrated circuits | Lee-Chung Lu, Yuan-Te Hou, Shyue-Shyh Lin, Dian-Hau Chen | 2015-08-25 |
| 9105466 | Integrated circuit | Lee-Chung Lu, Hui-Zhong Zhuang, Mei-Hui Huang | 2015-08-11 |
| 9098668 | Layout of an integrated circuit | Hui-Zhong Zhuang, Ting-Wei Chiang, Hsiang-Jen Tseng, Wei-Yu Chen | 2015-08-04 |
| 9087170 | Cell layout design and method | Chin-Hsiung Hsu, Yuan-Te Hou, Hui-Zhong Zhuang, Fang-Yu Fan, Wen-Hao Chen +1 more | 2015-07-21 |
| 9082886 | Adding decoupling function for tap cells | Kuo-Ji Chen | 2015-07-14 |
| 9064799 | Method of forming edge devices for improved performance | Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao | 2015-06-23 |
| 9041069 | Distributed metal routing | You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao | 2015-05-26 |
| 9035393 | Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration | Wei Ma, Bo-Ting Chen, Ting Yu Chen, Kuo-Ji Chen | 2015-05-19 |
| 9026971 | Multi-patterning conflict free integrated circuit design | Chien Lin Ho, Chin-Chang Hsu, Hung-Lung Lin, Wen-Ju Yang, Yi-Kan Cheng +5 more | 2015-05-05 |
| 9026973 | System and method for arbitrary metal spacing for self-aligned double patterning | Chen-Chi Wu, Kuo-Ji Chen | 2015-05-05 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang +2 more | 2014-12-09 |
| 8837250 | Method and apparatus for word line decoder layout | You-Cheng Xiao, Hong-Chen Cheng, Chung-Ji Lu, Cheng Hung Lee, Jung-Hsuan Chen | 2014-09-16 |
| 8819610 | Method and layout of an integrated circuit | Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ruei-Wun SUN, Hung-Jung Tseng +1 more | 2014-08-26 |
| 8816403 | Efficient semiconductor device cell layout utilizing underlying local connective features | Jung-Hsuan Chen, May-Hua Chang, Chiting Cheng | 2014-08-26 |
| 8813016 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang +2 more | 2014-08-19 |
| 8799834 | Self-aligned multiple patterning layout design | Huang-Yu Chen, Ken-Hsien Hsieh, Jhih-Jian Wang, Chin-Chang Hsu, Chin-Hsiung Hsu +3 more | 2014-08-05 |
| 8728892 | Adaptive fin design for FinFETs | Tsong-Hua Ou, Shu-Min Chen, Pin-Dai Sue, Ru-Gun Liu | 2014-05-20 |
| 8665654 | Memory edge cell | Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Cheng Hung Lee +1 more | 2014-03-04 |
| 8661389 | Systems and methods of designing integrated circuits | Chan-Hong Chern, Fu-Lung Hsueh | 2014-02-25 |
| 8631366 | Integrated circuit design using DFM-enhanced architecture | Yung-Chin Hou, Lee-Chung Lu, Yi-Kan Cheng, Chun-Hui Tai, Ta-Pen Guo +1 more | 2014-01-14 |
| 8610236 | Edge devices layout for improved performance | Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao | 2013-12-17 |
| 8607172 | Integrated circuits and methods of designing the same | Lee-Chung Lu, Hui-Zhong Zhuang, Mei-Hui Huang | 2013-12-10 |
| 8507957 | Integrated circuit layouts with power rails under bottom metal layer | Yung-Chin Hou, Shyue-Shyh Lin, Shu-Min Chen, Pin-Dai Sue | 2013-08-13 |