Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12273115 | Dual mode phase-locked loop circuit, oscillator circuit, and control method of oscillator circuit | YU-HSUN CHIEN | 2025-04-08 |
| 12229064 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Yueh-Chuan Lu | 2025-02-18 |
| 12174648 | Power management circuit and method for integrated circuit having multiple power domains | Chih-Chieh Yao, Chun-Hsiang Lai | 2024-12-24 |
| 12155143 | Current transmission assembly and current transmission system | XIANG-BIAO TANG, Yen-Lin Chen | 2024-11-26 |
| 12081231 | Configurable voltage regulator circuit and transmitter circuit | YU-HSUN CHIEN | 2024-09-03 |
| 11984899 | Dual mode phase-locked loop circuit, oscillator circuit, and control method of oscillator circuit | YU-HSUN CHIEN | 2024-05-14 |
| 11888252 | Current transmission assembly and current transmission system | XIANG-BIAO TANG, Yen-Lin Chen | 2024-01-30 |
| 11831285 | Load circuit of amplifier and driver circuit for supporting multiple interface standards | — | 2023-11-28 |
| 11799492 | Configurable voltage regulator circuit and transmitter circuit | YU-HSUN CHIEN | 2023-10-24 |
| 11648808 | Tire pressure sensor and burning device and burning method thereof | Ji-Liang Chen | 2023-05-16 |
| 11609872 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Yueh-Chuan Lu | 2023-03-21 |
| 11567516 | Power management circuit and method for integrated circuit having multiple power domains | Chih-Chieh Yao, Chun-Hsiang Lai | 2023-01-31 |
| 11414553 | Fouling-proof structure | Kuo-Hsing Yeh, Chun-Chieh Wang | 2022-08-16 |
| 11411574 | Clock and data recovery circuit with proportional path and integral path, and multiplexer circuit for clock and data recovery circuit | Cheng-Liang Hung | 2022-08-09 |
| 11211750 | Electrical connector assembly | Tsu-Yang Wu, Wei-Chou Lin | 2021-12-28 |
| 11055241 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Yueh-Chuan Lu | 2021-07-06 |
| 11012087 | Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof | Yueh-Chuan Lu | 2021-05-18 |
| 10886882 | Load circuit of amplifier and driver circuit for supporting multiple interface standards | — | 2021-01-05 |
| 10691017 | Pellicle for advanced lithography | Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Sheng-Chi Chin | 2020-06-23 |
| 10574431 | Physical layer circuitry for multi-wire interface | Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang | 2020-02-25 |
| 10541689 | Clock generation circuit and associated circuitry | Yu-Hsiang Chang | 2020-01-21 |
| 10506139 | Reconfigurable pin-to-pin interface capable of supporting different lane combinations and/or different physical layers and associated method | Li-Hung Chiueh, Man-Ju Lee, Chen-Yu Hsiao | 2019-12-10 |
| 10453677 | Method of forming oxide layer | Cheng-Hsu Huang, Jui-Min Lee, Yi-Wei Chen, Wei-Hsin Liu, Shih-Fang Tzou | 2019-10-22 |
| 10446559 | Method of fabricating DRAM | Tzu-Chin Wu, Chao Liu, Yi-Wei Chen | 2019-10-15 |
| 10396806 | Voltage regulator based loop filter for loop circuit and loop filtering method | Ming Ting Wu | 2019-08-27 |