Issued Patents All Time
Showing 101–125 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9099530 | Methods of patterning small via pitch dimensions | Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Hsiang-Lin Chen +2 more | 2015-08-04 |
| 8999839 | Semiconductor structure having an air-gap region and a method of manufacturing the same | Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu +1 more | 2015-04-07 |
| 9003336 | Mask assignment optimization | Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu +4 more | 2015-04-07 |
| 8975749 | Method of making a semiconductor device including barrier layers for copper interconnect | Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang +2 more | 2015-03-10 |
| 8786094 | Semiconductor devices and methods of manufacture thereof | Chung-Min Fu, Wen-Hao Chen | 2014-07-22 |
| 8728332 | Methods of patterning small via pitch dimensions | Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Hsiang-Lin Chen +2 more | 2014-05-20 |
| 8716862 | Integrated circuit including a gate and a metallic connecting line | Chii-Ping Chen | 2014-05-06 |
| 8653664 | Barrier layers for copper interconnect | Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang +2 more | 2014-02-18 |
| 8564103 | Method of manufacturing an electronic device | Bin-Yuan Hung, Sung-Hui Huang, Wen-Ting Tsai, Ching Wei Hsieh | 2013-10-22 |
| 8456009 | Semiconductor structure having an air-gap region and a method of manufacturing the same | Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu +1 more | 2013-06-04 |
| 8304906 | Partial air gap formation for providing interconnect isolation in integrated circuits | Cheng-Lin Huang, Jiing-Feng Yang, Chii-Ping Chen, Yuh-Jier Mii | 2012-11-06 |
| 8119310 | Mask-shift-aware RC extraction for double patterning design | Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh +2 more | 2012-02-21 |
| 7160811 | Laminated silicate glass layer etch stop method for fabricating microelectronic product | Yen-Ming Chen, Huan Chi Tseng, Yu-Hua Lee, Chia-Hung Lai, Kang-Min Kuo | 2007-01-09 |
| 7067896 | Microelectronic fabrication having edge passivated bond pad integrated with option selection device access aperture | Juei-Kuo Wu, Yi-Lang Wu, Lin-June Wu | 2006-06-27 |
| 6936408 | Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layer | Yong-Shun Liao, Juing-Yi Wu, Zhen-Cheng Chou | 2005-08-30 |
| 6929713 | In-situ photoresist removal by an attachable chamber with light source | Chiang-Jen Peng | 2005-08-16 |
| 6861376 | Photoresist scum free process for via first dual damascene process | Ruei-Je Shiu, Juei-Kuo Wu | 2005-03-01 |
| 6734116 | Damascene method employing multi-layer etch stop layer | Cheng Guo, Li-Kong Turn, Han-Ming Sheng | 2004-05-11 |
| 6667230 | Passivation and planarization process for flip chip packages | Lin-June Wu, Kwang-Ming Lin | 2003-12-23 |
| 6664194 | Photoexposure method for facilitating photoresist stripping | Chiang-Jen Peng, Wei-Kay Chiu | 2003-12-16 |
| 6652666 | Wet dip method for photoresist and polymer stripping without buffer treatment step | Ching-Tien Ma, Chen-Hsi Shih, Gau-Ming Lu, Cho-Ching Chen | 2003-11-25 |
| 6570257 | IMD film composition for dual damascene process | Ching-Tien Ma, Hsiang-Tan Lee | 2003-05-27 |
| 6551927 | CoSix process to improve junction leakage | Kwang-Ming Lin, Yu-Ku Lin, Tong-Hua Kuan, Jin-Kuen Lan | 2003-04-22 |
| 6489216 | Chemical mechanical polish (CMP) planarizing method employing topographic mark preservation | Ruei-Je Shiu | 2002-12-03 |
| 6468904 | RPO process for selective CoSix formation | Fu-Mei Chiu, Lin-June Wu | 2002-10-22 |