Issued Patents All Time
Showing 76–92 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6544874 | Method for forming junction on insulator (JOI) structure | Jack A. Mandelman, Kevin K. Chan, Oleg Gluschenkov, Rajarao Jammy, Victor Ku +2 more | 2003-04-08 |
| 6518614 | Embedded one-time programmable non-volatile memory using prompt shift device | Matthew J. Breitwisch, Chung H. Lam | 2003-02-11 |
| 6504207 | Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same | Jay G. Harrington, Kevin M. Houlihan, Dennis Hoyniak, Chung H. Lam, Hyun Koo Lee +2 more | 2003-01-07 |
| 6429091 | Patterned buried insulator | Alexander Hirsch, Sundar Iyer, Nivo Rovedo, Hsing-Jen Wann, Ying Zhang | 2002-08-06 |
| 6429101 | Method of forming thermally stable polycrystal to single crystal electrical contact structure | Ricky S. Amos, Arne Ballantine, Gregory Bazan, Douglas D. Coolbaugh, Ramachandra Divakaruni +6 more | 2002-08-06 |
| 6297127 | Self-aligned deep trench isolation to shallow trench isolation | Liang Han, Robert Hannon, Jay G. Harrington, Herbert L. Ho, Hsing-Jen Wann | 2001-10-02 |
| 6294449 | Self-aligned contact for closely spaced transistors | Teresa J. Wu, John W. Golz, Charles W. Koburger, III, Paul C. Parries, Christopher J. Waskiewicz +1 more | 2001-09-25 |
| 6294817 | Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication | Senthil Srinivasan | 2001-09-25 |
| 6287913 | Double polysilicon process for providing single chip high performance logic and compact embedded memory structure | Paul D. Agnello, Scott W. Crowder, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky | 2001-09-11 |
| 6238963 | Damascene process for forming ferroelectric capacitors | Chorng-Lii Hwang | 2001-05-29 |
| 6022766 | Semiconductor structure incorporating thin film transistors, and methods for its manufacture | Subhash B. Kulkarni, Jerome B. Lasky, Randy W. Mann, Edward J. Nowak, Werner Rausch +1 more | 2000-02-08 |
| 5675185 | Semiconductor structure incorporating thin film transistors with undoped cap oxide layers | Subhash B. Kulkarni, Jerome B. Lasky, Randy W. Mann, Edward J. Nowak, Werner Rausch +1 more | 1997-10-07 |
| 5665629 | Four transistor SRAM process | Gorden Seth Starkey, Jr. | 1997-09-09 |
| 5578854 | Vertical load resistor SRAM cell | Gorden Seth Starkey, Jr. | 1996-11-26 |
| 5562770 | Semiconductor manufacturing process for low dislocation defects | Terence B. Hook, Subhash B. Kulkarni | 1996-10-08 |
| 5556802 | Method of making corrugated vertical stack capacitor (CVSTC) | Paul E. Bakeman, Jr., John Cronin, Steven J. Holmes, Hing Wong | 1996-09-17 |
| 5538592 | Non-random sub-lithography vertical stack capacitor | Gary B. Bronner, Son V. Nguyen | 1996-07-23 |