Issued Patents All Time
Showing 51–75 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7119396 | NROM device | Dana Lee, Yaw Wen Hu, Bing Yeh | 2006-10-10 |
| 7050316 | Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements | Ya-Fen Lin, Elbert Lin, Dana Lee, Hung Quoc Nguyen | 2006-05-23 |
| 7012273 | Phase change memory device employing thermal-electrical contacts with narrowing electrical current paths | — | 2006-03-14 |
| 7012310 | Array of multi-bit ROM cells with each cell having bi-directional read and a method for making the array | Dana Lee | 2006-03-14 |
| 6992909 | Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array | Kai Man Yue, Dana Lee, Feng Gao | 2006-01-31 |
| 6958273 | Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby | Dana Lee | 2005-10-25 |
| 6950188 | Wafer alignment system using parallel imaging detection | Qiang Wu | 2005-09-27 |
| 6937507 | Memory device and method of operating same | — | 2005-08-30 |
| 6936883 | Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation | Jack Edward Frayer, Dana Lee | 2005-08-30 |
| 6927993 | Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells | Kai Man Yue, Dana Lee, Feng Gao | 2005-08-09 |
| 6927410 | Memory device with discrete layers of phase change memory material | — | 2005-08-09 |
| 6913975 | Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation | Dana Lee, Bing Yeh | 2005-07-05 |
| 6906379 | Semiconductor memory array of floating gate memory cells with buried floating gate | Dana Lee, Hieu Van Tran | 2005-06-14 |
| 6891169 | Electron beam array write head system and method | Scott Bukofsky, Sara Jennifer Eames, Qiang Wu | 2005-05-10 |
| 6873006 | Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region | Ying-Kit Tsui, Wen-Juei Lu | 2005-03-29 |
| 6870233 | Multi-bit ROM cell with bi-directional read and a method for making thereof | Kai Man Yue, Andrew Chen | 2005-03-22 |
| 6861315 | Method of manufacturing an array of bi-directional nonvolatile memory cells | Sohrab Kianian | 2005-03-01 |
| 6834009 | Integrated circuit with a three transistor reprogrammable nonvolatile switch for selectively connecting a source for a signal to a circuit | Kai Man Yue | 2004-12-21 |
| 6815704 | Phase change memory device employing thermally insulating voids | — | 2004-11-09 |
| 6809425 | Integrated circuit with a reprogrammable nonvolatile switch having a dynamic threshold voltage (VTH) for selectively connecting a source for a signal to a circuit | Isao Nojima, Hung Quoc Nguyen | 2004-10-26 |
| 6806531 | Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation | Dana Lee, Bing Yeh | 2004-10-19 |
| 6777260 | Method of making sub-lithographic sized contact holes | — | 2004-08-17 |
| 6773570 | Integrated plating and planarization process and apparatus therefor | Laertis Economikos, Hariklia Deligianni, John M. Cotte, Henry Grabarz | 2004-08-10 |
| 6756632 | Integrated circuit with a reprogrammable nonvolatile switch for selectively connecting a source for a signal to a circuit | Douglas J. Lee, Jack Edward Frayer, Kai Man Yue | 2004-06-29 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic | Paul D. Agnello, Scott W. Crowder, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky | 2004-02-03 |