Issued Patents All Time
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11914886 | Nonvolatile memory with on-chip encoding for foggy-fine programming | Sergey Anatolievich Gorobets | 2024-02-27 |
| 11650756 | Nonvolatile memory with encoding for foggy-fine programming with soft bits | Idan Alrod, Alexander Bazarsky, Tien-Chien Kuo, Eran Sharon, Sergey Anatolievich Gorobets | 2023-05-16 |
| 11495296 | Read threshold calibration for nonvolatile memory with encoded foggy-fine programming | Idan Alrod, Eran Sharon, Sergey Anatolievich Gorobets, Tien-Chien Kuo, Alexander Bazarsky | 2022-11-08 |
| 10114690 | Multi-die status mode for non-volatile storage | Grishma Shah | 2018-10-30 |
| 10032488 | System and method of managing data in a non-volatile memory having a staging sub-drive | Gulzar Kathawala, Sergey Anatolievich Gorobets, Kroum S. Stoev, Liam Michael Parker | 2018-07-24 |
| 9959078 | Multi-die rolling status mode for non-volatile storage | Grishma Shah, Aaron K. Olbrich, Chang Hua Siau, Vidyabhushan Mohan, Gopinath Balakrishnan +1 more | 2018-05-01 |
| 9864545 | Open erase block read automation | Robert W. Ellis, Vidyabhushan Mohan | 2018-01-09 |
| 9753653 | High-priority NAND operations management | Robert W. Ellis, Vidyabhushan Mohan, Todd Lindberg | 2017-09-05 |
| 9653184 | Non-volatile memory module with physical-to-physical address remapping | Vidyabhushan Mohan | 2017-05-16 |
| 9613715 | Low-test memory stack for non-volatile storage | Vidyabhushan Mohan | 2017-04-04 |
| 9367246 | Performance optimization of data transfer for soft information generation | Aaron K. Olbrich | 2016-06-14 |
| 9048876 | Systems, methods and devices for multi-tiered error correction | Aaron K. Olbrich | 2015-06-02 |
| 8976609 | Low-test memory stack for non-volatile storage | Vidyabhushan Mohan | 2015-03-10 |
| 8954822 | Data encoder and decoder using memory-specific parity-check matrix | Aaron K. Olbrich | 2015-02-10 |
| 8924815 | Systems, methods and devices for decoding codewords having multiple parity segments | Aaron K. Olbrich | 2014-12-30 |
| 8910020 | Intelligent bit recovery for flash memory | Aaron K. Olbrich, Paul Stonelake, Anand Kulkarni, Yale Yueh Ma | 2014-12-09 |
| 8780639 | Non-volatile memory device with plural reference cells, and method of setting the reference cells | Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov +3 more | 2014-07-15 |
| 8576630 | Non-volatile memory device with plural reference cells, and method of setting the reference cells | Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov +3 more | 2013-11-05 |
| 8559228 | Non-volatile memory device with plural reference cells, and method of setting the reference cells | Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov +3 more | 2013-10-15 |
| 7826267 | Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array | Ya-Fen Lin, Gianfranco Pellegrini, William Saiki, Changyuan Chen, Xiuhong Chen | 2010-11-02 |
| 7470949 | Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing | Bomy Chen, Yuniarto Widjaja, Felix (Ying-Kit) Tsui | 2008-12-30 |
| 7439572 | Stacked gate memory cell with erase to gate, array, and method of manufacturing | Bomy Chen, Hieu Van Tran, Dana Lee | 2008-10-21 |
| 7403418 | Word line voltage boosting circuit and a memory array incorporating same | Ya-Fen Lin, Elbert Lin, Hieu Van Tran, Bomy Chen | 2008-07-22 |
| 7242050 | Stacked gate memory cell with erase to gate, array, and method of manufacturing | Bomy Chen, Hieu Van Tran, Dana Lee | 2007-07-10 |
| 7227217 | Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing | Amitay Levi, Pavel Klinger, Bomy Chen, Hieu Van Tran, Dana Lee | 2007-06-05 |