Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7547603 | Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same | Bomy Chen, Yaw Wen Hu | 2009-06-16 |
| 7537996 | Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate | Yaw Wen Hu | 2009-05-26 |
| 7533063 | Smart memory card wallet | — | 2009-05-12 |
| 7411246 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby | — | 2008-08-12 |
| 7326614 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby | — | 2008-02-05 |
| 7307308 | Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation | Dana Lee, Bomy Chen | 2007-12-11 |
| 7205198 | Method of making a bi-directional read/program non-volatile floating gate memory cell | Bomy Chen, Jack Edward Frayer | 2007-04-17 |
| 7190018 | Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation | Bomy Chen, Jack Edward Frayer | 2007-03-13 |
| 7144778 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line | Chih-Hsin Wang | 2006-12-05 |
| 7129536 | Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same | Bomy Chen, Yaw Wen Hu | 2006-10-31 |
| 7074672 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor | Chih-Hsin Wang | 2006-07-11 |
| 6952034 | Semiconductor memory array of floating gate memory cells with buried source line and floating gate | Yaw Wen Hu | 2005-10-04 |
| 6952033 | Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line | Chih-Hsin Wang | 2005-10-04 |
| 6940125 | Vertical NROM and methods for making thereof | Dana Lee | 2005-09-06 |
| 6917069 | Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor | Chih-Hsin Wang | 2005-07-12 |
| 6891220 | Method of programming electrons onto a floating gate of a non-volatile memory cell | Bing Yeh, Yaw Wen Hu | 2005-05-10 |
| 6861315 | Method of manufacturing an array of bi-directional nonvolatile memory cells | Bomy Chen | 2005-03-01 |
| 5852577 | Electrically erasable and programmable read-only memory having a small unit for program and erase | Dana Lee | 1998-12-22 |