Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12150393 | Heater for phase change material memory cell | Jin-Ping Han, Samuel S. Choi, Injo Ok | 2024-11-19 |
| 11309221 | Single metallization scheme for gate, source, and drain contact integration | Andrew M. Greene, Gangadhara Raja Muthinti | 2022-04-19 |
| 11257716 | Self-aligned gate cap including an etch-stop layer | Michael P. Belyansky, Marc A. Bergendahl, Jeffrey C. Shearer | 2022-02-22 |
| 11222820 | Self-aligned gate cap including an etch-stop layer | Michael P. Belyansky, Marc A. Bergendahl, Jeffrey C. Shearer | 2022-01-11 |
| 10985076 | Single metallization scheme for gate, source, and drain contact integration | Andrew M. Greene, Gangadhara Raja Muthinti | 2021-04-20 |
| 10943990 | Gate contact over active enabled by alternative spacer scheme and claw-shaped cap | Andrew M. Greene, Gangadhara Raja Muthinti, Veeraraghavan S. Basker, Junli Wang, Kisik Choi +1 more | 2021-03-09 |
| 10229984 | Gap fill of metal stack in replacement gate process | Jin-Ping Han, Shangbin Ko | 2019-03-12 |
| 10217839 | Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET | Chanro Park, Kisup Chung, Koji Watanabe | 2019-02-26 |
| 10043744 | Avoiding gate metal via shorting to source or drain contacts | Xuefeng Liu, Yann Mignot, Yongan Xu | 2018-08-07 |
| 9935174 | Gap fill of metal stack in replacement gate process | Jin-Ping Han, Shangbin Ko | 2018-04-03 |
| 9929250 | Semiconductor device including optimized gate stack profile | Jin-Ping Han | 2018-03-27 |
| 9837351 | Avoiding gate metal via shorting to source or drain contacts | Xuefeng Liu, Yann Mignot, Yongan Xu | 2017-12-05 |
| 9748358 | Gap fill of metal stack in replacement gate process | Jin-Ping Han, Shangbin Ko | 2017-08-29 |
| 9355887 | Dual trench isolation for CMOS with hybrid orientations | Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-Yung Sung, Min Yang | 2016-05-31 |
| 8969969 | High threshold voltage NMOS transistors for low power IC technology | Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan, Roger A. Booth, Jr. | 2015-03-03 |
| 8927361 | High threshold voltage NMOS transistors for low power IC technology | Roger A. Booth, Jr., Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan | 2015-01-06 |
| 8753929 | Structure fabrication method | Brent A. Anderson, Edward J. Nowak | 2014-06-17 |
| 8466503 | Semiconductor transistors with expanded top portions of gates | Brent A. Anderson, Edward J. Nowak | 2013-06-18 |
| 8338245 | Integrated circuit system employing stress-engineered spacers | Jae Gon Lee, Jong-ho Yang, Jun Jung Kim | 2012-12-25 |
| 8148221 | Double anneal with improved reliability for dual contact etch stop liner scheme | Khee Yong Lim, Eng Hua Lim, Wenhe Lin, Jamin F. Fen | 2012-04-03 |
| 8097516 | Dual trench isolation for CMOS with hybrid orientations | Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-Yung Sung, Min Yang | 2012-01-17 |
| 8012821 | Semiconductor embedded resistor generation | Choongryul Ryou, Seunghwan Lee, Jun Yuan, Manfred Eller, Nam Sung Kim +2 more | 2011-09-06 |
| 7943486 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Massimo V. Fischetti, John Michael Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek +3 more | 2011-05-17 |
| 7816909 | Mechanical stress characterization in semiconductor device | Khee Yong Lim | 2010-10-19 |
| 7659174 | Method to enhance device performance with selective stress relief | Yong Meng Lee, Haining Yang | 2010-02-09 |