Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308284 | Plug and trench architectures for integrated circuits and methods of manufacture | Charles H. Wallace, Marvin Young Paik, Hyunsoo Park, Mohit K. HARAN, Alexander F. Kaplan | 2025-05-20 |
| 11764219 | Metal space centered standard cell architecture to enable higher cell density | Harshitha Vishwanath, Renukprasad HIREMATH, Sukru YEMENICIOGLU, Ranjith Kumar | 2023-09-19 |
| 11723188 | Replacement metal COB integration process for embedded DRAM | Uygar E. Avci, Ian A. Young, Daniel H. Morris, Seiyon Kim, Yih Wang | 2023-08-08 |
| 11652045 | Via contact patterning method to increase edge placement error margin | Mohit K. HARAN, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An +6 more | 2023-05-16 |
| 11417567 | Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom | Florian Gstrein, Eungnak Han, Rami Hourani, Paul A. Nyhus, Manish Chandhok +2 more | 2022-08-16 |
| 11322504 | Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technology | Uygar E. Avci, Daniel H. Morris, Seiyon Kim, Yih Wang, Ian A. Young | 2022-05-03 |
| 11211324 | Via contact patterning method to increase edge placement error margin | Mohit K. HARAN, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An +6 more | 2021-12-28 |
| 11171043 | Plug and trench architectures for integrated circuits and methods of manufacture | Charles H. Wallace, Marvin Young Paik, Hyunsoo Park, Mohit K. HARAN, Alexander F. Kaplan | 2021-11-09 |
| 11145541 | Conductive via and metal line end fabrication and structures resulting therefrom | Charles H. Wallace, Reken Patel, Hyunsoo Park, Mohit K. HARAN, Debashish Basu +1 more | 2021-10-12 |
| 11068640 | Power shared cell architecture | Ranjith Kumar, Mark Bohr, Marni Nabors, Tai-Hsuan Wu, Sourav Chakravarty | 2021-07-20 |
| 10943817 | Etch-stop layer topography for advanced integrated circuit structure fabrication | Andrew W. Yeoh, Michael L. Hattendorf, Christopher P. Auth | 2021-03-09 |
| 10903114 | Decoupled via fill | Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri | 2021-01-26 |
| 10811595 | Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory | Kevin J. Lee, Oleg Golonzka, Tahir Ghani, Yih Wang | 2020-10-20 |
| 10796951 | Etch-stop layer topography for advanced integrated circuit structure fabrication | Andrew W. Yeoh, Michael L. Hattendorf, Christopher P. Auth | 2020-10-06 |
| 10672650 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Mark Bohr | 2020-06-02 |
| 10593626 | AVD hardmask for damascene patterning | Kevin J. Fischer, Michael A. Childs | 2020-03-17 |
| 10535601 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Mark Bohr, Manish Chandhok | 2020-01-14 |
| 10468298 | Decoupled via fill | Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri | 2019-11-05 |
| 10211098 | Decoupled via fill | Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri | 2019-02-19 |
| 10032643 | Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme | Jasmeet S. Chawla, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers | 2018-07-24 |
| 10032857 | Etchstop layers and capacitors | — | 2018-07-24 |
| 10026649 | Decoupled via fill | Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri | 2018-07-17 |
| 9899255 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Mark Bohr | 2018-02-20 |
| 9780038 | AVD hardmask for damascene patterning | Kevin J. Fischer, Michael A. Childs | 2017-10-03 |
| 9607992 | Etchstop layers and capacitors | — | 2017-03-28 |