Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10811305 | Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management | Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang, Bucknell C. Webb | 2020-10-20 |
| 10615139 | Semiconductor device including built-in crack-arresting film structure | Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2020-04-07 |
| 10211178 | Semiconductor device including built-in crack-arresting film structure | Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2019-02-19 |
| 10020279 | Semiconductor device including built-in crack-arresting film structure | Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2018-07-10 |
| 9865469 | Epitaxial lift-off process with guided etching | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-01-09 |
| 9653308 | Epitaxial lift-off process with guided etching | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2017-05-16 |
| 9536853 | Semiconductor device including built-in crack-arresting film structure | Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2017-01-03 |
| 9355936 | Flattened substrate surface for substrate bonding | Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles S. Musante, BethAnn Rainey Lawrence +2 more | 2016-05-31 |
| 8927968 | Accurate control of distance between suspended semiconductor nanowires and substrate surface | Guy M. Cohen, Michael A. Guillorn, Alfred Grill | 2015-01-06 |
| 8927405 | Accurate control of distance between suspended semiconductor nanowires and substrate surface | Guy M. Cohen, Michael A. Guillorn, Alfred Grill | 2015-01-06 |
| 8877606 | Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation | Robert H. Dennard, David R. Greenberg, Amlan Majumdar, Jeng-Bang Yau | 2014-11-04 |
| 8778737 | Flattened substrate surface for substrate bonding | Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles F. Musante, BethAnn Rainey +2 more | 2014-07-15 |
| 8637381 | High-k dielectric and silicon nitride box region | Effendi Leobandung, Dae-Gyu Park, Shom Ponoth, Zhibin Ren, Ghavam G. Shahidi | 2014-01-28 |
| 8586426 | Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box | Robert H. Dennard, Marwan H. Khater, Jeng-Bang Yau | 2013-11-19 |
| 8492838 | Isolation structures for SOI devices with ultrathin SOI and ultrathin box | Robert H. Dennard, Marwan H. Khater, Jeng-Bang Yau | 2013-07-23 |
| 8408262 | Adaptive chuck for planar bonding between substrates | Dechao Guo, Fei Liu, Keith Kwong Hon Wong | 2013-04-02 |
| 8030145 | Back-gated fully depleted SOI transistor | Leland Chang, Brian L. Ji, Arvind Kumar, Amlan Majumdar, Katherine L. Saenger +1 more | 2011-10-04 |
| 8017499 | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) | Kevin K. Chan, Jack O. Chu, Kern Rim | 2011-09-13 |
| 7897480 | Preparation of high quality strained-semiconductor directly-on-insulator substrates | Jack O. Chu, Alexander Reznicek, Philip A. Saunders | 2011-03-01 |
| 7767546 | Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer | Robert H. Dennard, David R. Greenberg, Amian Majumdar, Jeng-Bang Yau | 2010-08-03 |
| 7713837 | Low temperature fusion bonding with high surface energy using a wet chemical treatment | Kevin K. Chan, Kathryn Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Dinkar Singh | 2010-05-11 |
| 7704815 | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques | Jack O. Chu, Michael A. Cobb, Philip A. Saunders | 2010-04-27 |
| 7691688 | Strained silicon CMOS on hybrid crystal orientations | Kevin K. Chan, Meikei Ieong, Alexander Reznicek, Devendra K. Sadana, Min Yang | 2010-04-06 |
| 7566631 | Low temperature fusion bonding with high surface energy using a wet chemical treatment | Kevin K. Chan, Kathryn Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Dinkar Singh | 2009-07-28 |
| 7528056 | Low-cost strained SOI substrate for high-performance CMOS technology | Meikei Ieong, Douglas C. La Tulipe, Jr., Anna W. Topol, James Vichiconti, Albert M. Young | 2009-05-05 |