Issued Patents All Time
Showing 451–475 of 534 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7541629 | Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process | Haizhou Yin, Zhijiong Luo | 2009-06-02 |
| 7528027 | Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel | Mahender Kumar, Dan M. Mocuta, Ravikumar Ramachandran, Wenjuan Zhu | 2009-05-05 |
| 7528451 | CMOS gate conductor having cross-diffusion barrier | Thomas W. Dyer, Haining Yang | 2009-05-05 |
| 7521307 | CMOS structures and methods using self-aligned dual stressed layers | Daewon Yang | 2009-04-21 |
| 7504309 | Pre-silicide spacer removal | Thomas W. Dyer, Sunfei Fang, Jiang Yan, Jun Jung Kim, Yaocheng Liu | 2009-03-17 |
| 7504696 | CMOS with dual metal gate | Zhijiong Luo, Dae-Gyu Park | 2009-03-17 |
| 7504693 | Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering | Bruce B. Doris, Huajie Chen | 2009-03-17 |
| 7498602 | Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets | Bruce B. Doris, Dan M. Mocuta | 2009-03-03 |
| 7485520 | Method of manufacturing a body-contacted finfet | Thomas W. Dyer, Jack A. Mandelman, Werner Rausch | 2009-02-03 |
| 7485524 | MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same | Zhijiong Luo, Yung Fu Chong, Judson R. Holt, Zhao Lun | 2009-02-03 |
| 7485521 | Self-aligned dual stressed layers for NFET and PFET | Brian L. Tessier, Huicai Zhong | 2009-02-03 |
| 7485510 | Field effect device including inverted V shaped channel region and method for fabrication thereof | Ravikumar Ramachandran, Effendi Leobandung, Mahender Kumar, Wenjuan Zhu, Christine Norris | 2009-02-03 |
| 7482656 | Method and structure to form self-aligned selective-SOI | Zhijiong Luo, Yung Fu Chong, Kevin K. Dezfulian, Judson R. Holt | 2009-01-27 |
| 7482615 | High performance MOSFET comprising stressed phase change material | — | 2009-01-27 |
| 7476579 | Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film | Jing Wang, Bruce B. Doris, Zhibin Ren | 2009-01-13 |
| 7476580 | Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C | Bruce B. Doris, Huajie Chen | 2009-01-13 |
| 7462915 | Method and apparatus for increase strain effect in a transistor channel | Haining Yang | 2008-12-09 |
| 7456636 | Test structures and method of defect detection using voltage contrast inspection | Oliver D. Patterson | 2008-11-25 |
| 7452761 | Hybrid SOI-bulk semiconductor transistors | Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen +1 more | 2008-11-18 |
| 7446004 | Method for reducing overlap capacitance in field effect transistors | Oleg Gluschenkov | 2008-11-04 |
| 7442619 | Method of forming substantially L-shaped silicide contact for a semiconductor device | Zhijiong Luo, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo | 2008-10-28 |
| 7442585 | MOSFET with laterally graded channel region and method for manufacturing same | Xiangdong Chen | 2008-10-28 |
| 7439110 | Strained HOT (hybrid orientation technology) MOSFETs | Kangguo Cheng, Woo-Hyeong Lee | 2008-10-21 |
| 7436006 | Hybrid strained orientated substrates and devices | Kangguo Cheng | 2008-10-14 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels | Bruce B. Doris, Huajie Chen, Patricia M. Mooney, Stephen W. Bedell | 2008-09-09 |