Issued Patents All Time
Showing 476–500 of 534 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7416986 | Test structure and method for detecting via contact shorting in shallow trench isolation regions | Shih-Fen Huang, Effendi Leobandung | 2008-08-26 |
| 7413961 | Method of fabricating a transistor structure | Yung Fu Chong, Kevin K. Dezfulian, Zhijiong Luo | 2008-08-19 |
| 7410852 | Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors | Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Sunfei Fang, Brian J. Greene +6 more | 2008-08-12 |
| 7397081 | Sidewall semiconductor transistors | Lawrence A. Clevenger, Omer H. Dokumaci, Kaushik A. Kumar, Carl Radens, Dureseti Chidambarrao | 2008-07-08 |
| 7393751 | Semiconductor structure including laminated isolation region | Zhijiong Luo | 2008-07-01 |
| 7388257 | Multi-gate device with high k dielectric for channel top surface | Bruce B. Doris, Oleg Gluschenkov, Ying Zhang | 2008-06-17 |
| 7385258 | Transistors having v-shape source/drain metal contacts | Haining Yang, Zhijiong Luo | 2008-06-10 |
| 7381609 | Method and structure for controlling stress in a transistor channel | Haining Yang | 2008-06-03 |
| 7354806 | Semiconductor device structure with active regions having different surface directions and methods | Bruce B. Doris, Oleg Gluschenkov, Meikei Ieong, Effendi Leobandung | 2008-04-08 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors | Oleg Gluschenkov | 2008-04-08 |
| 7348635 | Device having enhanced stress state and related methods | Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha, Haining Yang | 2008-03-25 |
| 7348641 | Structure and method of making double-gated self-aligned finFET having gates of different lengths | Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges | 2008-03-25 |
| 7348225 | Structure and method of fabricating FINFET with buried channel | — | 2008-03-25 |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines | — | 2008-03-04 |
| 7326997 | Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film | Jing Wang, Bruce B. Doris, Zhibin Ren | 2008-02-05 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification | Cyril Cabral, Jr., Bruce B. Doris, Thomas S. Kanarsky, Xiao Hu Liu | 2008-01-01 |
| 7314802 | Structure and method for manufacturing strained FINFET | Bruce B. Doris | 2008-01-01 |
| 7312134 | Dual stressed SOI substrates | Dureseti Chidambarrao, Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov | 2007-12-25 |
| 7309901 | Field effect transistors (FETs) with multiple and/or staircase silicide | Xiangdong Chen, Sunfei Fang, Zhijiong Luo, Haining Yang | 2007-12-18 |
| 7288451 | Method and structure for forming self-aligned, dual stress liner for CMOS devices | Huicai Zhong, Effendi Leobandung | 2007-10-30 |
| 7288443 | Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension | — | 2007-10-30 |
| 7285826 | High mobility CMOS circuits | Bruce B. Doris, Oleg Gluschenkov | 2007-10-23 |
| 7282435 | Method of forming contact for dual liner product | Haining Yang, Clement Wann | 2007-10-16 |
| 7271043 | Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels | Bruce B. Doris, Huajie Chen, Patricia M. Mooney, Stephen W. Bedell | 2007-09-18 |
| 7271442 | Transistor structure having stressed regions of opposite types underlying channel and source/drain regions | Haining Yang | 2007-09-18 |