HZ

Huilong Zhu

IBM: 237 patents #122 of 70,183Top 1%
CM Chartered Semiconductor Manufacturing: 5 patents #123 of 840Top 15%
BT Beijing Superstring Academy Of Memory Technology: 3 patents #12 of 37Top 35%
AM AMD: 2 patents #3,994 of 9,279Top 45%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
CT China University Of Mining And Technology: 1 patents #288 of 815Top 40%
BC Beijing Nmc Co.: 1 patents #3 of 20Top 15%
📍 Poughkeepsie, NY: #1 of 1,613 inventorsTop 1%
🗺 New York: #22 of 115,490 inventorsTop 1%
Overall (All Time): #333 of 4,157,543Top 1%
534
Patents All Time

Issued Patents All Time

Showing 501–525 of 534 patents

Patent #TitleCo-InventorsDate
7268049 Structure and method for manufacturing MOSFET with super-steep retrograded island Effendi Leobandung, Anda C. Mocuta, Dan M. Mocuta 2007-09-11
7262087 Dual stressed SOI substrates Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov, Omer H. Dokumaci 2007-08-28
7262084 Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom Bruce B. Doris 2007-08-28
7256081 Structure and method to induce strain in a semiconductor device channel with stressed film under the gate Haining Yang 2007-08-14
7253482 Structure for reducing overlap capacitance in field effect transistors Oleg Gluschenkov 2007-08-07
7247547 Method of fabricating a field effect transistor having improved junctions Oleg Gluschenkov, Chun-Yung Sung 2007-07-24
7244644 Undercut and residual spacer prevention for dual stressed layers Brian L. Tessier, Huicai Zhong, Ying Li 2007-07-17
7224033 Structure and method for manufacturing strained FINFET Bruce B. Doris 2007-05-29
7223994 Strained Si on multiple materials for bulk or SOI substrates Dureseti Chidambarrao, Omer H. Dokumaci, Oleg Gluschenkov 2007-05-29
7224021 MOSFET with high angle sidewall gate and contacts for reduced miller capacitance Dureseti Chidambarrao, Lawrence A. Clevenger, Omer H. Dokumaci, Kaushik A. Kumar 2007-05-29
7220626 Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels Bruce B. Doris, Philip J. Oldiges, Meikei Ieong, Min Yang, Huajie Chen 2007-05-22
7220662 Fully silicided field effect transistors Sunfei Fang, Zhijiong Luo 2007-05-22
7211490 Ultra thin channel MOSFET Bruce B. Doris, Thomas S. Kanarsky, Ying Zhang, Meikei Ieong, Omer H. Dokumaci 2007-05-01
7202132 Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs Bruce B. Doris, Dan M. Mocuta 2007-04-10
7183613 Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film Jing Wang, Bruce B. Doris, Zhibin Ren 2007-02-27
7173312 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification Cyril Cabral, Jr., Bruce B. Doris, Thomas S. Kanarsky, Xiao Hu Liu 2007-02-06
7163867 Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom Kam-Leung Lee 2007-01-16
7118999 Method and apparatus to increase strain effect in a transistor channel Haining Yang 2006-10-10
7105440 Self-forming metal silicide gate for CMOS devices Zhijiong Luo, Sunfei Fang 2006-09-12
7106096 Circuit and method of controlling integrated circuit power consumption using phase change switches Hon-Sum Philip Wong, Xinlin Wang, David R. Hanson 2006-09-12
7098536 Structure for strained channel field effect transistor pair having a member and a contact via Haining Yang, Clement Wann 2006-08-29
7098477 Structure and method of manufacturing a finFET device having stacked fins Bruce B. Doris 2006-08-29
7094634 Structure and method for manufacturing planar SOI substrate with multiple orientations Bruce B. Doris, Meikei Ieong, Phillip J. Oldiges, Min Yang 2006-08-22
7091566 Dual gate FinFet Jochen Beintner, Bruce B. Doris, Ying Zhang 2006-08-15
7087952 Dual function FinFET, finmemory and method of manufacture Bruce B. Doris, Jochen Beintner 2006-08-08