Issued Patents All Time
Showing 76–87 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7417315 | Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging | Gareth G. Hougham, S. Jay Chey, James P. Doyle, Christopher V. Jahnes, Paul A. Lauro +2 more | 2008-08-26 |
| 7394089 | Heat-shielded low power PCM-based reprogrammable EFUSE device | James P. Doyle, Bruce G. Elmegreen, Lia Krusin-Elbaum, Chung H. Lam, Dennis M. Newns +1 more | 2008-07-01 |
| 7388273 | Reprogrammable fuse structure and method | Geoffrey Burr, Chandrasekharan Kothandaraman, Chung H. Lam, Stephen M. Rossnagel, Christy S. Tyberg +1 more | 2008-06-17 |
| 7371684 | Process for preparing electronics structures using a sacrificial multilayer hardmask scheme | Matthew E. Colburn, Ricardo A. Donaton, Conal E. Murray, Satyanarayana V. Nitta, Sampath Purushothaman +2 more | 2008-05-13 |
| 7357977 | Ultralow dielectric constant layer with controlled biaxial stress | Christos D. Dimitrakopoulos, Stephen M. Gates, Alfred Grill, Michael Lane, Eric G. Liniger +3 more | 2008-04-15 |
| 7335980 | Hardmask for reliability of silicon based dielectrics | Son V. Nguyen, Michael Lane, Stephen M. Gates, Vincent J. McGahay, Sanjay C. Mehta +1 more | 2008-02-26 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification | Cyril Cabral, Jr., Bruce B. Doris, Thomas S. Kanarsky, Huilong Zhu | 2008-01-01 |
| 7276787 | Silicon chip carrier with conductive through-vias and method for fabricating same | Daniel C. Edelstein, Paul S. Andry, Leena Paivikki Buchwalter, Jon A. Casey, Sherif A. Goma +9 more | 2007-10-02 |
| 7260810 | Method of extracting properties of back end of line (BEOL) chip architecture | Ronald G. Filippi, Giovanni Fiorenza, Conal E. Murray, Gregory A. Northrop, Thomas M. Shaw +2 more | 2007-08-21 |
| 7173312 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification | Cyril Cabral, Jr., Bruce B. Doris, Thomas S. Kanarsky, Huilong Zhu | 2007-02-06 |
| 7067902 | Building metal pillars in a chip for structure support | Habib Hichri, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw | 2006-06-27 |
| 6972209 | Stacked via-stud with improved reliability in copper metallurgy | Birendra Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane +8 more | 2005-12-06 |