Issued Patents All Time
Showing 126–150 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6969903 | High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature | Ebenezer E. Eshun | 2005-11-29 |
| 6956266 | Structure and method for latchup suppression utilizing trench and masked sub-collector implantation | Anne E. Watson | 2005-10-18 |
| 6946707 | Electrostatic discharge input and power clamp circuit for high cutoff frequency technology radio frequency (RF) applications | — | 2005-09-20 |
| 6943578 | Method and application of PICA (picosecond imaging circuit analysis) for high current pulsed phenomena | Naoko Pia Sanda, Alan J. Weger | 2005-09-13 |
| 6895372 | System and method for VLSI visualization | Daniel R. Knebel, Mark A. Lavin, Jamie H. Moreno, Stanislav Polonsky, Pia Naoko Sanda | 2005-05-17 |
| 6891207 | Electrostatic discharge protection networks for triple well semiconductor devices | James P. Pequignot, Jeffrey H. Sloan, Douglas W. Stout | 2005-05-10 |
| 6878976 | Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications | Douglas D. Coolbaugh | 2005-04-12 |
| 6838323 | Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure | Robert J. Gauthier, Jr., Edward J. Nowak, Xiaowei Tian, Minh H. Tong | 2005-01-04 |
| 6826025 | Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit | Raminderpal Singh | 2004-11-30 |
| 6774017 | Method and structures for dual depth oxygen layers in silicon-on-insulator processes | Jeffrey S. Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy W. Mann | 2004-08-10 |
| 6762918 | Fault free fuse network | — | 2004-07-13 |
| 6750109 | Halo-free non-rectifying contact on chip with halo source/drain diffusion | James A. Culp, Jawahar P. Nayak, Werner Rausch, Melanie J. Sherony, Noah Zamdmer | 2004-06-15 |
| 6746947 | Post-fuse blow corrosion prevention structure for copper fuses | Timothy H. Daubenspeck, Daniel C. Edelstein, Robert M. Geffken, William T. Motsiff, Anthony K. Stamper | 2004-06-08 |
| 6731488 | Dual emitter transistor with ESD protection | — | 2004-05-04 |
| 6725439 | Method of automated design and checking for ESD robustness | Philip S. Homsinger, Andrew D. Huber, Debra K. Korejwa, William J. Livingstone, Jeannie H. Panner +3 more | 2004-04-20 |
| 6720637 | SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks | — | 2004-04-13 |
| 6710983 | ESD protection for GMR sensors of magnetic heads using SiGe integrated circuit devices | — | 2004-03-23 |
| 6704179 | Automated hierarchical parameterized ESD network design and checking system | — | 2004-03-09 |
| 6700164 | Tungsten hot wire current limiter for ESD protection | Ciaran J. Brennan, Kevin A. Duncan, William R. Tonti | 2004-03-02 |
| 6680520 | Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses | Anthony K. Stamper | 2004-01-20 |
| 6670654 | Silicon germanium heterojunction bipolar transistor with carbon incorporation | Louis D. Lanzerotti, Brian P. Ronan | 2003-12-30 |
| 6635548 | Capacitor and method for forming same | Kerry Bernstein, Nicholas Theodore Schmidt, Anthony K. Stamper, Stephen A. St. Onge | 2003-10-21 |
| 6628159 | SOI voltage-tolerant body-coupled pass transistor | — | 2003-09-30 |
| 6600199 | Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity | Robb Johnson, Louis D. Lanzerotti, Stephen A. St. Onge | 2003-07-29 |
| 6586818 | Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement | — | 2003-07-01 |